參數(shù)資料
型號: SC16C752
廠商: NXP Semiconductors N.V.
英文描述: Dual UART with 64-byte FIFO
中文描述: 雙UART具有64字節(jié)FIFO
文件頁數(shù): 26/47頁
文件大?。?/td> 604K
代理商: SC16C752
Philips Semiconductors
SC16C752
Dual UART with 64-byte FIFO
Product data
Rev. 04 — 20 June 2003
26 of 47
9397 750 11635
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
[1]
IER[7:4] can only be modified if EFR[4] is set, i.e., EFR[4] is a write enable. Re-enabling IER[1] will
not cause a new interrupt if the THR is below the threshold.
7.9 Interrupt identification register (IIR)
The IIR is a read-only 8-bit register which provides the source of the interrupt in a
prioritized manner.
Table 17
shows interrupt identification register bit settings.
The interrupt priority list is shown in
Table 18
.
4
IER[4]
[1]
Sleep mode.
Logic 0 = Disable sleep mode (normal default condition).
Logic 1 = Enable sleep mode. See
Section 6.7 “Sleep mode”
for details.
Modem Status Interrupt.
Logic 0 = Disable the modem status register interrupt (normal default
condition).
Logic 1 = Enable the modem status register interrupt.
Receive Line Status interrupt.
Logic 0 = Disable the receiver line status interrupt (normal default
condition).
Logic 1 = Enable the receiver line status interrupt.
Transmit Holding Register interrupt.
Logic 0 = Disable the THR interrupt (normal default condition).
Logic 1 = Enable the THR interrupt.
Receive Holding Register interrupt.
Logic 0 = Disable the RHR interrupt (normal default condition).
Logic 1 = Enable the RHR interrupt.
3
IER[3]
2
IER[2]
1
IER[1]
0
IER[0]
Table 16:
Bit
Interrupt Enable Register bits description
…continued
Symbol
Description
Table 17:
Bit
7-6
5
4
3-1
0
Interrupt Identification Register bits description
Symbol
Description
IIR[7:6]
Mirror the contents of FCR[0].
IIR[5]
RTS/CTS LOW-to-HIGH change of state.
IIR[4]
1 = Xoff/Special character has been detected.
IIR[3:1]
3-bit encoded interrupt. See
Table 18
.
IIR[0]
Interrupt status.
Logic 0 = An interrupt is pending.
Logic 1 = No interrupt is pending.
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