參數(shù)資料
型號： SAF7849HL
廠商： NXP Semiconductors N.V.
元件分類： 存儲器
英文描述： One chip CD audio device with integrated MP3-WMA decoder
封裝： SAF7843HL/M295<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,;SAF7849HL/M245<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.h
文件頁數(shù)： 76/93頁
文件大小： 396K
代理商： SAF7849HL
SAF784X_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2008
76 of 93
NXP Semiconductors
SAF784x
One chip CD audio device with integrated MP3/WMA decoder
For memory-to-memory transfers, the length of the operation is specified. When half of
this length is reached, or when the end of the transfer has been reached, the CPU can be
interrupted or the CPU can poll for notification of this event.
The SDMA controller has a maximum of six channels, each channel can be configured
with its own source, destination, length and control information.
The SDMA controller is primarily dedicated from sector transfers from segmentation
manager to the ARM sub-system RAM.
Performs memory-to-memory copies in two AHB cycles, and memory-to-peripheral or
peripheral-to-memory in three AHB cycles
Supports byte, half-word and word transfers, and correctly aligns it over the AHB bus
Compatible with ARM flow control, for single requests (sreq), last single requests
(lsreq), terminal count info (tc) and DMA clearing (clr)
SAF784x architecture supports little endian for data transfers
Contains maskable interrupts for each raw IRQ
7.15 Back-end audio processing
The back-end audio processing entails the parallel-to-serial I
2
S conversion, sample-rate
conversion for MP3 decoding and EBU data format generation.
7.15.1
Parallel-to-serial I
2
S conversion
Can operate in both master and slave modes
Capable of handling NXP I
2
S format of 8-bit, 16-bit and 32-bit word sizes
Mono and stereo audio data supported
The sampling frequency can range (in practice) from 16 kHz to 48 kHz (16 kHz,
22.05 kHz, 32 kHz, 44.1 kHz or 48 kHz)
Two FIFOs are provided as data buffers, one for transmitting and one for reception;
the depth of these FIFOs is configurable in HDLi
Generates interrupt request
Generates two DMA requests
Controls include reset, stop, and mute options
DMA acknowledge signals
7.15.2
Variable sample-rate converter
The hardware sample-rate conversion receives inputs from a varying input source. The
input is an I
2
S stereo audio signal. The sample-rate conversion block converts the
frequency into a fixed 44.1 kHz audio output signal. The block works at a fixed frequency:
16.9344 MHz (384
×
44.1 kHz, or 67.7376 MHz / 4).
The audio input frequencies can range from 8 kHz to 48 kHz. The block converts the I
2
S
input signal to a signal with a fixed sampling frequency of 44.1 kHz.
The incoming I
2
S signal is stored in a buffer. The signal is upsampled by a variable
upsampling factor N. After a variable hold, the signal is down-converted with a fixed
down-sample factor M.
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相關代理商/技術參數(shù)
參數(shù)描述
SAF7849HL/M245,557 功能描述:音頻 DSP IC AUD DECODER RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube
SAF7849HL/M295,557 功能描述:音頻 DSP IC AUD DECODER RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube
SAF7860HL/M2,557 制造商:NXP Semiconductors 功能描述:DSP
SAF82520PVB2 制造商:SIEMENS 功能描述:New
SAF82525 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Data Communications ICs
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