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參數(shù)資料
| 型號： | SAF7849HL |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 存儲器 |
| 英文描述： | One chip CD audio device with integrated MP3-WMA decoder |
| 封裝： | SAF7843HL/M295<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,;SAF7849HL/M245<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.h |
| 文件頁數(shù)： | 44/93頁 |
| 文件大?。?/td> | 396K |
| 代理商： | SAF7849HL |
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SAF784X_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2008
44 of 93
NXP Semiconductors
SAF784x
One chip CD audio device with integrated MP3/WMA decoder
I
2
S bclk and I
2
S wclk can either be input (generated outside the channel decoder) or
output (generated internally in the clock control block). Selection can be done via WclkSel
and BclkSel in register I2SConfig.
The I
2
S output rate is determined by the speed of the I
2
S bclk clock, which is configured
via register BitClockConfig. One can configure the I
2
S interface to run at 1
×
CD speed or
2
×
CD speed.
For a gated bit clock, when BitClockConfig bit BCLKGEN is HIGH, the speed must be
configured such that the maximum rate available on the bus is 20 % higher than the
average data throughput rate i.e. the bus should have at least 20 % idle time between two
bursts of data.
Default after reset, the I
2
S pins on the IC will be put into 3-state. They can be activated via
register I2SConfig. This register also contains the possibility to ‘kill’ the I
2
S interface, such
that all data lines output a constant ‘0’.
6.5.9.10
Subcode (V4) interface
Subcode data is output via the I
2
S subO (V4) port. This data can be sampled using the I
2
S
sync signal (see
Section 6.5.9.9 on page 43
). The sync indicates that the serial subcode
line (V4) contains the MSB of a subcode word; it will be asserted every six wclk-periods
for half a wclk-period. If a subcode sync is transferred on the subcode line, this signal will
be asserted for a full wclk period.
During normal operation (upsampling disabled), the subcode output via I
2
S subO will have
the format as shown in
Figure 24
.
When upsampling is enabled, the I
2
S interface runs at four times the non-upsampled rate.
The subcode bit period however will stay at the bit period of the non-upsampled rate as
shown in
Figure 25
. This means that the I
2
S subO and I
2
S sync signal will appear to be
four times slower relative to I
2
S wclk. In this case the receiver must use I
2
S wclk divided
by 4 to sample the subcode.
Fig 24. Subcode output (upsampling disabled)
001aag328
wclk
1 subcode byte every 24 I
2
S data bytes
V4
sync
b7
(start)
(start)
b6
b5
b4
b7
b6
b5
b4
b3
b2
b1
b0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAF7849HL/M245,557 | 功能描述:音頻 DSP IC AUD DECODER RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| SAF7849HL/M295,557 | 功能描述:音頻 DSP IC AUD DECODER RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| SAF7860HL/M2,557 | 制造商:NXP Semiconductors 功能描述:DSP |
| SAF82520PVB2 | 制造商:SIEMENS 功能描述:New |
| SAF82525 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Data Communications ICs |
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