參數(shù)資料
型號： SAF7849HL
廠商： NXP Semiconductors N.V.
元件分類： 存儲(chǔ)器
英文描述： One chip CD audio device with integrated MP3-WMA decoder
封裝： SAF7843HL/M295<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,;SAF7849HL/M245<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.h
文件頁數(shù)： 67/93頁
文件大?。?/td> 396K
代理商： SAF7849HL
SAF784X_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2008
67 of 93
NXP Semiconductors
SAF784x
One chip CD audio device with integrated MP3/WMA decoder
[1]
The frequency of operation depends on the performance required for the SAA7834 application and the
software complexity. MP3/WMA decoding requires most high-speed peripherals to operate at this
frequency. The MP3/WMA decoding library is implemented in software.
The ARM7TDMI-S processor has two instruction sets:
1. The 32-bit ARM instruction set
2. The 16-bit ARM thumb instruction
The ARM uses a three-stage pipeline to increase the throughput of the flow of instructions
to the processor. This enables several operations to operate simultaneously and the
processor and memory systems to operate continuously.
The three-stage pipelines can be defined in the following stages:
Fetch cycle: fetches the instruction from the memory
Decode cycle: decodes the registers and the instructions fetched
Execute cycle: fetches the data from register banks; the shift, ALU operations
performed and data is written back to the memory
The microprocessors have traditionally the same width for the instructions and data. The
32-bit architecture would be more efficient in performance and could also address a much
larger address space compared to 16-bit architectures. The code density for 16-bit
architecture would be much higher than 32-bit and the performance would be greater than
half the 32-bit performance.
The ARM thumb instructions concept addresses the issues when 16-bit instructions are
used but the performance required is 32-bit architecture. Therefore the aim of the thumb
instruction set can be summarized as follows:
Higher performance for 16-bit architecture, if 16-bit instructions are to be used.
The code density achieved with 16-bit instructions in a 32-bit architecture is the most
efficient use of memory space.
7.2 Static Memory Interface Unit (SMIU)
The AHB SRAM controller implements an AHB slave interface to an external SRAM. This
interface is only available in the development version of this device. The specification of
this interface is described below:
32-bit AHB interface width
76 MHz maximum AHB operating frequency
Configured for low latency
Maximum of two SRAMs/ROMs/Flash/Burst ROM of 2 MB each, can be accessible
32-bit data
Table 15.
Process
technology
Performance characteristics for ARM7TDMI-S
Performance
(MIPS/MHz)
(mW/MHz)
Power consumption
Maximum operating
frequency (MHz)
Typical operating
frequency
requirements for
SAF784x (MHz)
76
[1]
0.18
μ
m
0.9
0.39
76
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