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SAF784X_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2008
25 of 93
NXP Semiconductors
SAF784x
One chip CD audio device with integrated MP3/WMA decoder
The maximum and minimum peaks on the envelope of the RF signal after the ADC are
first measured via a noise filter and the window peak detector (see
Section “Peak
Detectors” on page 23
. The amplitude is then calculated as maxpeak
minpeak, and the
offset as (maxpeak + minpeak) / 2.
For tuning the loops, it is possible to read back the HFMaxPeak, HFMinPeak,
HFAmplitude and HFOffset, as measured from their registers by the decay peak detector.
AGC control:
The RF amplitude at the ADC input can be changed with two gain
amplifiers in the analog part: G1 (fixed) and G2 (dynamic). G1 has a gain range from 0 dB
to 24 dB in 16 steps of 1.6 dB, while G2 has a range from 0 dB to 12 dB in 16 steps of 0.8
dB. Both gains can be programmed via register AGCGain. G1 will stay fixed, while G2 can
be regulated by hardware when the AGC is turned on.
The AGC will regulate the gain such that the measured amplitude stays between a
programmed upper threshold (AGCThrHi) and lower threshold (AGCThrLo). If the
amplitude is smaller, gain will increase; if the amplitude is too large, gain will decrease.
When clipping is detected on either one or both sides, the gain will decrease. These gain
changes are not sent to the analog gain amplifier directly but are integrated over time.
Only if, on average, a gain increase or decrease is requested, will this result in a real gain
increase or decrease of the amplifier. This can also be read back via register AGCGain.
The AGC, together with the noise filter on the peak detector, prevents RF noise causing
over-sensitive gain regulation. To further reduce sensitive behavior, a hysteresis window
with a width of one gain step is added between the integrator and amplifier G2. The
bandwidth of the gain loop determines how fast it reacts to fingerprints and scratches; it is
programmed via register AGCIntegBW. It is also possible to limit the range of G2 by
programming a maximum and minimum boundary by register AGCGainBound.
AOC control:
Most of the RF offset at the ADC input will be removed by the analog HPF
(1st-order HPF with 3 dB point around 3.6 kHz). The remaining offset (mainly introduced
by the analog front end), can be removed by adding or subtracting a fixed offset in the
analog part. This offset subtraction/addition has a range of 32 steps in each direction, with
approximately 1.4 LSBs per step (referenced to the RF ADC). This leads to a full
Fig 14. AGC and AOC loops
001aag318
HPF
(DIGITAL)
6 MSBs
K gain
software/
defect
INTEGRATOR
lo
hi
1
+1
1
+1
to bit detection
G1
G2
G3
HPF
ANALOG
DEFECT
DETECT
REGISTERS
INTEGRATOR
CLIPPING
DETECT
DECAY
PEAK
DETECTOR
WINDOW
PEAK
DETECTOR
DECAY
PEAK
DETECTOR
INTEGRATE
AND
DUMP
FILTER
NF
(LPF)
NF
(LPF)
ADC
K offset
software/
defect
lo
hi
4 MSBs