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參數(shù)資料
| 型號： | SAF7849HL |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 存儲器 |
| 英文描述： | One chip CD audio device with integrated MP3-WMA decoder |
| 封裝： | SAF7843HL/M295<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,;SAF7849HL/M245<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.h |
| 文件頁數(shù)： | 64/93頁 |
| 文件大?。?/td> | 396K |
| 代理商： | SAF7849HL |
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SAF784X_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2008
64 of 93
NXP Semiconductors
SAF784x
One chip CD audio device with integrated MP3/WMA decoder
The alignment between the main channel and the subcode channel must be the same
each time a sector is read.
6.8.3
Block decoder to segmentation manager interface
The MiMeD2 interface is the data interface between the block decoder and the SAF784x
segment manager. It is an asynchronous interface; the block decoder and SAF784x
segment manager operate in independent clock domains.
Data is transferred over MiMeD2 in bursts of one sector. The size and speed of the
transfer is determined by the settings in the OP_CTRL register. Each transaction on
MiMeD2 is accompanied by a toggle of the bld_req signal. The data and flags are updated
on each transaction.
The transfer order is:
1. Main data: 1176 word16 (2352 bytes)
2. Flags data (optional): 148 word16 (296 bytes)
3. Subcode data (optional): 57 word16 (114 bytes)
4. Status words: two word16 (four bytes)
6.9 Segmentation manager
6.9.1
General
The segmentation manager controls the flow of block-decoded data from the block
decoder and synchronous ARM system bus.
The segmentation manager consists of a 2 kB buffer, that is accessible on the ARM
subsystem bus once the entire sector has been transferred from block decoder into the
segmentation buffer.
The DMA cycle is then initiated to transfer sector data from the segmentation manager to
the ARM processor memory for MP3 decoding to commence. The DMA transfers are
expected to be continuous burst transfers to ARM processor memory and completed at
the sector boundary.
The segmentation manager register SEL_WRITE_MODE allows access to the
segmentation buffer either to the block decoder MiMeD interface or the synchronous ARM
system bus.
Remark:
Access to segmentation buffer from the MiMeD interface is Write access only, or
Access only from synchronous ARM processor system bus is Read access only.
The segmentation buffer memory is 692-bit SRAM
×
32-bit SRAM. The maximum number
of 32-bit words per complete sector is 692 words.
6.9.2
Interrupt generation
An interrupt is generated on completion of transfer of every sector from the block decoder.
The signal memory_full is used to generate an interrupt. The interrupt, once serviced by
software, can be cleared by register write to Inreq_Clr.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAF7849HL/M245,557 | 功能描述:音頻 DSP IC AUD DECODER RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAF7849HL/M295,557 | 功能描述:音頻 DSP IC AUD DECODER RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAF7860HL/M2,557 | 制造商:NXP Semiconductors 功能描述:DSP |
| SAF82520PVB2 | 制造商:SIEMENS 功能描述:New |
| SAF82525 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Data Communications ICs |
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