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參數(shù)資料
| 型號： | SAF7846HL |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 存儲器 |
| 英文描述： | One chip CD audio device with integrated MP3-WMA decoder |
| 封裝： | SAF7843HL/M295<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,;SAF7849HL/M245<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.h |
| 文件頁數(shù)： | 75/93頁 |
| 文件大?。?/td> | 396K |
| 代理商： | SAF7846HL |
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SAF784X_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2008
75 of 93
NXP Semiconductors
SAF784x
One chip CD audio device with integrated MP3/WMA decoder
7.11 Timers
Conforms to the VLSI Peripheral Bus (VPB) interface specification
Clock prescaler for external high-frequency sources
The VPB timer operates in two fully independent clock domains:
–
vpb_clk for accessing control and status registers (76 MHz maximum)
–
timer_clk for the timer/counter function (50 MHz maximum)
The VPB timer can support up to four match registers having:
–
Continuous operation with optional interrupt generation on match
–
Stop on match, with or without, interrupt generation
–
Reset on match, with or without, interrupt generation
Optional external match notification pins with the following features:
–
Set LOW on match
–
Set HIGH on match
–
Toggle on match
–
No action on match
Up to four capture registers and capture trigger pins with optional interrupt generation
on a capture event
Interrupt generation on match event and capture event
7.12 Watchdog timer
Configurable watchdog feature including:
–
Watchdog timer restart trigger protection by key
–
Watchdog timer reload value protection by key access sequence
–
Watchdog timer reset disable (for debug) protection by key
Interrupt generation watchdog time-out event
7.13 Real-time clock
Zero wait-state to access all registers from the VPB interface
Provide coherent fraction and seconds time
Requirement for external 32 kHz crystal
Alarm and tick interrupts will be generated even when the VPB clock is switched off
VPB RTC interrupt
Real-time clock and VPB clock may be asynchronous (the VPB clock frequency could
be higher or lower than the RTC clock frequency)
Maximum VPB slave frequency: 50 MHz
7.14 DMA controller
The Single operation DMA interface (SDMA), is a small AHB bus master specifically
designed for bulk memory transfers over the ARM AHB bus.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAF7846HL/M210,557 | 功能描述:音頻 DSP 1 chip CD Audio Dev w/Integrated decoder RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAF7847HL/M201,557 | 功能描述:音頻 DSP 1 chip CD Audio Dev w/Integrated decoder RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAF7849HL/M245,557 | 功能描述:音頻 DSP IC AUD DECODER RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAF7849HL/M295,557 | 功能描述:音頻 DSP IC AUD DECODER RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAF7860HL/M2,557 | 制造商:NXP Semiconductors 功能描述:DSP |
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