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參數(shù)資料
| 型號： | SAF7846HL |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 存儲器 |
| 英文描述： | One chip CD audio device with integrated MP3-WMA decoder |
| 封裝： | SAF7843HL/M295<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,;SAF7849HL/M245<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.h |
| 文件頁數(shù)： | 12/93頁 |
| 文件大?。?/td> | 396K |
| 代理商： | SAF7846HL |
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SAF784X_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2008
12 of 93
NXP Semiconductors
SAF784x
One chip CD audio device with integrated MP3/WMA decoder
To help users set up the correct gain and DC offset for each particular mechanism, an eye
pattern monitor facility is included. This consists of a high frequency buffer amplifier
whose input can be selected to monitor various important nodes within the analog RF
path. The monitor point is controlled by register RFControl1[6:4] field RFMONSEL. The
output of the buffer drives HF_MON pin (pin 7). This register also controls the roll-off
frequency of the noise filter which is in front of the 6-bit ADC in the RF path.
Various blocks within the analog RF path can be powered down if required, including the
complete path. These power-down bits are controlled by register RFControl2[5:0].
In addition, the 6-bit RF ADC can be stand-alone tested in application mode, or a separate
external RF path IC can be connected to SAA7834 by selecting bit 1 of register
RFBypassSel. The input for the RF signal is then via pin HF_MON. In this mode the
central diode summing circuit, RF AMP1, high-pass filter and RF AMP2 are all bypassed.
6.2 Analog clock generation
The SAF784x consists of two analog phase-locked loops. The 67 MHz PLL is dedicated to
the channel decoder. The 152 MHz PLL is dedicated to the remaining functionality. The
clock strategy for the SAF784x is intended to address areas that are prone to noise effects
Fig 5.
Analog clock generation
001aag309
CLOCK MULTIPLIER
VARIABLE RATIO
OSC
register CLKGEN
CNTRL[4]
0
1
HF
ADC
AUDIO
DAC
CLOCK MULTIPLIER
8
×
÷
2
register CLKGEN
CNTRL[5]
register CLKGEN
CNTRL[1]
register CLKGEN
CNTRL[2]
register CLKGEN
CNTRL[3]
0
1
register
AnaClockPLLControl[3]
used for internal test
adac_in_8_clk
used for internal test
sys32k_clk
(real time clock)
micro_clk (152 MHz)
lfadc8m_clk
(digital servo)
pad_clk1v8
(used for
internal test)
register
AnaClockPLLControl[0]
ANALOG to DIGITAL
interface
PADS
pad_clk3v3
0
1
register CLKGEN
CNTRL[0]
0
1
OSC
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAF7846HL/M210,557 | 功能描述:音頻 DSP 1 chip CD Audio Dev w/Integrated decoder RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAF7847HL/M201,557 | 功能描述:音頻 DSP 1 chip CD Audio Dev w/Integrated decoder RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAF7849HL/M245,557 | 功能描述:音頻 DSP IC AUD DECODER RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAF7849HL/M295,557 | 功能描述:音頻 DSP IC AUD DECODER RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAF7860HL/M2,557 | 制造商:NXP Semiconductors 功能描述:DSP |
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