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參數(shù)資料
| 型號： | SAF7846HL |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 存儲器 |
| 英文描述： | One chip CD audio device with integrated MP3-WMA decoder |
| 封裝： | SAF7843HL/M295<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,;SAF7849HL/M245<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.h |
| 文件頁數(shù)： | 72/93頁 |
| 文件大?。?/td> | 396K |
| 代理商： | SAF7846HL |
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SAF784X_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2008
72 of 93
NXP Semiconductors
SAF784x
One chip CD audio device with integrated MP3/WMA decoder
Maximum ARM operating frequency for the SAF784x: for applications supporting
WMA decoding, the ARM operating frequency is fixed at 76 MHz
External memory access times: critical for determining the allowable delay that is to
be programmed via software, or the delay through the hardware
The equation for read latency delay for sequential reads. This is the worst case latency,
with no burst reads:
Memory address delay to external memory = one internal clock cycle.
External memory data to internal ARM = two internal cycle delay (fixed).
Additional delay, to increased set-up times; maximum delay is given as follows:
–
two internal cycles (fixed by hardware) + 31
×
cycle time (ARM processor
frequency).
–
31 cycles: the value that can be programmed in either register SMBWST1x or
SMBWST2x.
7.3 Program ROM interface
The ROM interface provides an interface between the on-board 130 kB ROM memory and
the ARM via the AHB bus. The interface specification is described below:
32-bit AHB interface width
76 MHz maximum AHB operating frequency
Configured for low latency
32-bit data
AMBA AHB-compliant
The low-latency architecture is optimized for low-speed operation. No wait-states are used
and the ROM control signals are taken directly from the AHB bus. This means that the
maximum frequency is likely to be limited by the speed at which the control signals arrive
from the AHB master.
7.4 Boot ROM interface
The ROM interface provides an interface between the on-board 42 kB ROM memory and
the ARM via the AHB bus. The interface specification is described below:
32-bit AHB interface width
76 MHz maximum AHB operating frequency
Configured for low latency
32-bit data
AMBA AHB-compliant
The low-latency architecture is optimized for low-speed operation. No wait-states are used
and the ROM control signals are taken directly from the AHB bus. This means that the
maximum frequency is likely to be limited by the speed at which the control signals arrive
from the AHB master.
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| SAF7847HL | One chip CD audio device with integrated MP3-WMA decoder |
| SAF7849HL | One chip CD audio device with integrated MP3-WMA decoder |
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAF7846HL/M210,557 | 功能描述:音頻 DSP 1 chip CD Audio Dev w/Integrated decoder RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| SAF7847HL/M201,557 | 功能描述:音頻 DSP 1 chip CD Audio Dev w/Integrated decoder RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| SAF7849HL/M245,557 | 功能描述:音頻 DSP IC AUD DECODER RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| SAF7849HL/M295,557 | 功能描述:音頻 DSP IC AUD DECODER RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| SAF7860HL/M2,557 | 制造商:NXP Semiconductors 功能描述:DSP |
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