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參數(shù)資料
| 型號： | SAF7846HL |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 存儲器 |
| 英文描述： | One chip CD audio device with integrated MP3-WMA decoder |
| 封裝： | SAF7843HL/M295<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,;SAF7849HL/M245<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.h |
| 文件頁數(shù)： | 33/93頁 |
| 文件大?。?/td> | 396K |
| 代理商： | SAF7846HL |
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SAF784X_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2008
33 of 93
NXP Semiconductors
SAF784x
One chip CD audio device with integrated MP3/WMA decoder
Analog preamplifier
ADC
Limited bandwidths in this device
Limited PLL performance
Influenced by internal noise filter, asymmetry compensation and equalizer
The jitter measurement is absolute reference, because it relates directly to the EFM bit
error rate if the disc noise is gaussian.
6.5.5.7
Internal lock flags
The fourth signal that can be monitored are three flags in the PLLLockStatus register: the
internally generated inner lock signal FLock, the internally generated lock signal InLock
and a LongSym(bol) flag when run length 14 is detected (run length too high).
In automatic mode, the FLock and InLock flags determine what type of PLL capture aid is
used.
6.5.5.8
Format of the measurements signal Meas1 on pin CL1
This signal is output via pin CL1 (pin 97) and comprises three measurement signals
multiplexed together. The format is shown in
Figure 18
and
Table 8
.
The data is sent in a serial format. It consists of a pause, followed by a start bit, followed
by data bits.
Bit length: four system clock periods; frame length: 64 bits.
Table 7.
FLock flag
0
1
x
Determining the current PLL capture mode
InLock flag
0
0
1
Capture mode
outer-lock aid
inner-lock aid
in-lock
Fig 18. Format on measurement pin CL1
Table 8.
Bit
0
1 to 10
11
12
13 to 22
23
24
25 to 32
33, 34, 35
Data format on measurement pin CL1
Value
'1'
jitter(9) to jitter(0)
'0'
'1'
pllfreq(9) to pllfreq(0)
'0'
'1'
asym(7) to asym(0)
'0'
Description
start bit
[1]
first sample of jitter word
[2]
intermediate start bit
PLL frequency word
intermediate start bit
slicer level
‘000’
001aag322
pause
start bit
data bits
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAF7846HL/M210,557 | 功能描述:音頻 DSP 1 chip CD Audio Dev w/Integrated decoder RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAF7847HL/M201,557 | 功能描述:音頻 DSP 1 chip CD Audio Dev w/Integrated decoder RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAF7849HL/M245,557 | 功能描述:音頻 DSP IC AUD DECODER RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAF7849HL/M295,557 | 功能描述:音頻 DSP IC AUD DECODER RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAF7860HL/M2,557 | 制造商:NXP Semiconductors 功能描述:DSP |
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