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參數(shù)資料
| 型號： | SAF7846HL |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 存儲器 |
| 英文描述： | One chip CD audio device with integrated MP3-WMA decoder |
| 封裝： | SAF7843HL/M295<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,;SAF7849HL/M245<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.h |
| 文件頁數(shù)： | 20/93頁 |
| 文件大?。?/td> | 396K |
| 代理商： | SAF7846HL |
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SAF784X_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2008
20 of 93
NXP Semiconductors
SAF784x
One chip CD audio device with integrated MP3/WMA decoder
xclk: most internal clocks are derived from the crystal clock. This clock is the output of
the clock multiplier in the analog part and has a fixed frequency of 67.7376 MHz
= 8.4672 MHz (f
xtal
)
×
8. If a 16 MHz crystal is used, the crystal clock is divided by 2
inside the analog block. Crystal selection is done via AnalPLLControl bit SEL16.
sysclk domain: the system clock, or its derivatives, runs the main part of the internal
channel decoder. The sysclk is derived from xclk divided by 2 (50 % duty cycle) and
can be further divided down via register SysclockConfig bit SYSDIV. This register also
allows the majority of clocks to be powered down (for Sleep mode). The choice of the
sysclk frequency f
clk(sys)
in an application is determined by the expected input bit rate
f
bit
of the RF bit stream. The relationship between this incoming bit stream frequency
and the system clock frequency f
clk(sys)
is expressed by the ratio f
bit
/ f
clk(sys)
. There are
two limiting factors:
–
The HF-PLL operating range is between 0.25
×
(f
bit
/ f
clk(sys)
) and 2
×
(f
bit
/ f
clk(sys)
)
–
The decoder and error corrector throughput rate is limited to 1.7
×
(f
bit
/ f
clk(sys)
)
This brings the constraint to 0.25 < f
bit
/ f
clk(sys)
< 1.7.
bitclk domain: runs the I
2
S back-end logic. The bit clock (bitclk) is also output as part
of the I
2
S interface. In audio slave mode this clock must be programmed to be exactly
44100 Hz
×
2
×
16/24/32 (depending on I
2
S mode), to get a 1
×
data rate to the audio
DAC. In master mode with gated bitclk, the bitclk must be programmed to be at a
higher rate than the outgoing bit rate required for the disc speed, to avoid FIFO
overflow in the decoder. For example, at N = 1, the incoming RF bit rate =
4.3218 MHz, which corresponds to an output bit rate of 1.4112 MHz. This means that
the bitclk frequency is above 1.4112 MHz and is high enough when I
2
S-16 is chosen,
while I
2
S-32 requires the bitclk to be at least 2.8224 MHz. The bitclk division is
selected via register BitClockConfig. Also, bitclk gating can be enabled via the same
register.
ebuclk domain: runs the EBU back end. The EBU (or S/PDIF) interface is only
enabled during audio slave mode. The ebuclk needs to be exactly
44100 Hz
×
64 = 2.8224 MHz for 1
×
operation. The ebuclk division is selected via
register EBUClockConfig.
The following clocks are also controlled by the clock control block:
–
The hf_clk is fixed at 67.7376 MHz, and is used to clock-in the samples from the
ADC, which is clocked by the xclk with the same clock frequency
–
The bclk_in is the incoming I
2
S bit clock, which is used when I
2
S is programmed to
receive bclk rather than transmitting it (programmed via register I2SConfig)
–
The cl1clk can be used to monitor the Cflg and Meas1 debug lines. The frequency
can be programmed via register CLClockConfig
–
The cl16clk can be used to clock an external audio DAC or audio filter IC. The
frequency can be programmed via register CLClockConfig
6.5.4
Decoder-ARM microprocessor interface
The decoder core is internally connected to the ARM core via the AHB interface for
register access to the decoder internal configuration registers.
6.5.4.1
Programming interface
Decoder registers are programmed through the AHB interface. The programming
interface is not fully described in this document.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAF7846HL/M210,557 | 功能描述:音頻 DSP 1 chip CD Audio Dev w/Integrated decoder RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| SAF7847HL/M201,557 | 功能描述:音頻 DSP 1 chip CD Audio Dev w/Integrated decoder RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| SAF7849HL/M245,557 | 功能描述:音頻 DSP IC AUD DECODER RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| SAF7849HL/M295,557 | 功能描述:音頻 DSP IC AUD DECODER RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| SAF7860HL/M2,557 | 制造商:NXP Semiconductors 功能描述:DSP |
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