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| 型號： | SAF7846HL |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 存儲器 |
| 英文描述： | One chip CD audio device with integrated MP3-WMA decoder |
| 封裝： | SAF7843HL/M295<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,;SAF7849HL/M245<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.h |
| 文件頁數(shù)： | 28/93頁 |
| 文件大小： | 396K |
| 代理商： | SAF7846HL |
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SAF784X_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2008
28 of 93
NXP Semiconductors
SAF784x
One chip CD audio device with integrated MP3/WMA decoder
6.5.5.2
Bit detector
The bit detector block contains the slice-level circuitry, a noise filter to limit HF EFM signal
noise contribution, an equalizer, a zero-transition detector, a run-length push-back circuit,
a digital PLL and jitter measurement logic.
All processing is performed on the bit clock, and bandwidths are proportional to the
channel bit rate. To achieve this, RF data is resampled from the system clock domain to
the bitclk domain by making use of a sample-rate convertor. Blocks can be configured
under microcontroller control and are described in detail in the next paragraphs.
Noise filter:
The digital noise filter runs on the channel bit clock frequency f
clk(bit)ch
. It
limits the bandwidth of the incoming signal to
1
4
of the channel bit clock frequency.
Passband: 0
×
f
clk(bit)ch
to 0.22
×
f
clk(bit)ch
(Hz)
Stop-band: (0.28
×
f
clk(bit)ch
) to (f
clk(bit)ch
0.28
×
f
clk(bit)ch
) (Hz)
Rejection:
28 dB
Slice-level determination:
The slice-level determination circuit compensates for the
incoming signal asymmetry component. Bandwidth of the slice-level determination circuit
is programmable via register SlicerBandwidth. Also the higher bandwidths for use after a
defect (see
Section “Defect detector” on page 26
) are programmed in this register. The
bandwidth is proportional to the channel bit clock frequency. The slice level, or asymmetry,
can be read back via register SlicerAssym.
Equalizer:
In the bit detection circuit, a programmable equalizer is used to boost the high
frequency content of the incoming signal.
The equalizer includes an integral five-tap presentable, asymmetrical equalizer. The
equalizer block diagram is given in
Figure 16
.
Fig 15. Bit detector block diagram
001aag319
clocked on
PLL clock
multiplex
to demodulator
Meas1
jitter value
PLL frequency
from
signal
conditioning
slice level
SRC
NOISE
FILTER
DIGITAL
PLL
RMS
JITTER
MEASUREMENT
RL2
PUSHBACK
DIGITAL
EQUALIZER
SLICE
LEVEL
DETERMINE
ZERO
TRANSITION
DETECT
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAF7846HL/M210,557 | 功能描述:音頻 DSP 1 chip CD Audio Dev w/Integrated decoder RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAF7847HL/M201,557 | 功能描述:音頻 DSP 1 chip CD Audio Dev w/Integrated decoder RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAF7849HL/M245,557 | 功能描述:音頻 DSP IC AUD DECODER RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAF7849HL/M295,557 | 功能描述:音頻 DSP IC AUD DECODER RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAF7860HL/M2,557 | 制造商:NXP Semiconductors 功能描述:DSP |
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