參數(shù)資料
型號: SAA7780
廠商: NXP SEMICONDUCTORS
元件分類: 消費(fèi)家電
英文描述: ThunderBird Q3DE PCI Audio Accelerator(雷鳥 Q3DE PCI音頻加速器)
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP160
封裝: 28 X 28 MM, 3.42 MM HEIGHT, PLASTIC, QFP-160
文件頁數(shù): 51/70頁
文件大?。?/td> 348K
代理商: SAA7780
ThunderBird Q3D PCI Audio
Accelerator
SAA7780
Philips Semiconductors
Product Specification
1999 Sep 30
51
Header Type Register - HEADER (RO)
BIST Register - BIST (RO)
SAA7780 CFG Space 1 Legacy Base Address Registers
The SAA7780, contains one legacy I/O base registers in configuration space 1. The joystick is the sole legacy I/O base
address register and is documented here.
Bit
Name
R/W
Function
7:0
LATIME
RO
The primary bus latency timer specifies the number of primary clocks that the
primary master may consume. It is set to zero since the joystick is a target
only.
PCI CFG 1
D7
D6
D5
D4
D3
D2
D1
D0
Offset 0Eh
MULTI_
FN
HEADER[6:0]
POR Value
1
0
0
0
0
0
0
0
Bit
Name
R/W
Function
7
MULTI_FN
RO
For the SAA7780, function 1, this bit has no meaning.
6:0
HEADER
RO
Header Type. A 00h indicates this device is not a PCI-to-PCI bridge.
PCI CFG 1
D7
D6
D5
D4
D3
D2
D1
D0
Offset 0Fh
BIST
START
R
R
CODE[3:0]
POR Value
0
0
0
0
0
0
0
0
Bit
Name
R/W
Function
7
BIST
RO
BIST capable. BIST is not supported in the SAA7780, function 1 at this
revision.
6
START
RO
If BIST capable, this bit will start the BIST. Writing a 1 will start the test and
the BIST should write this bit to a zero when complete. Software should fail
the device if the BIST is not complete after 2 seconds.
5:4
R
RO
Reserved. These bits always return zero.
3:0
CODE
RO
Completion Code. A value of zero means the device has passed its test.
Non-zero values means the device has failed using device specific failure
codes.
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