參數(shù)資料
型號: SAA7780
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: ThunderBird Q3DE PCI Audio Accelerator(雷鳥 Q3DE PCI音頻加速器)
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP160
封裝: 28 X 28 MM, 3.42 MM HEIGHT, PLASTIC, QFP-160
文件頁數(shù): 25/70頁
文件大?。?/td> 348K
代理商: SAA7780
ThunderBird Q3D PCI Audio
Accelerator
SAA7780
Philips Semiconductors
Product Specification
1999 Sep 30
25
Legend:
C
AGND
DGND
I
IO
O
APWR
DPWR
T
PD
CMOS-compatible input
Analog ground
Digital ground pin
Input-only pin (can become bidirectional for test mode)
Bidirectional pin
Output-only pin (can become bidirectional for test mode)
Analog power supply pin
Digital power supply pin
TTL-compatible input
Indicates a high-impedance with approximately 10 K minimum resistance to VSS (internal pull-down
resistor on pin)
Indicates a high-impedance with approximately 10 K minimum resistance to VDD (internal pull-up resis-
tor on pin)
Inidcates that this pin needs an external pull-up resistor when the chip is installed on a board or tester. A
10K ohm resistor is nominal
Indicates a Schmitt-trigger input with hysteresis for noise immunity
Three-state pin
Sustained three-state output / TTL input (if applicable)
Open drain pad
Analog based I/O. Use a pad with ESD protection
Core power. Denotes a pad that supplies power for the core of the chip only
Core ground. Denotes a pad that supplies ground to the core only
Ring power. Denotes a pad that supplies power to the pads only
Ring ground. Denotes a pad that supplies ground to the ring only
Ring power with option to power core level shifter. Denotes a pad that supplies power to the ring while its
core side connector can optionally supply internal level shifters
Ring/core ground. Denotes a pad that supple a ground connection to the ring and core
High impedance. When in a three state test mode, this pin will be forced into a high impedance state
Nand tree. When in a NAND tree test mode, this pin will be included in the parametric NAND tree logic
Nand tree output. When in a NAND tree test mode, this pin is the output of the parametric NAND tree
Function System Block test. Denotes that his pin is not timing critical and is available for FSB multiplexing
PU
PUB
S
TS
STS
OD
A
CP
CG
RP
RG
RPD
RCG
HZ
NT
NTO
FSB
VDD
1,142,28,41,
54,68,80,96,
112,121,135,
142
DPWR
Ring Power
VWELL
117
DPWR
External N-Well Bias
Tie these pins to 5V for proper 5 volt tolerant operation. The 5V
supply must be powered up before the 3V supply. Likewise, the 3V
supply must be powered down before the 5V supply.
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