參數(shù)資料
型號: SAA7780
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: ThunderBird Q3DE PCI Audio Accelerator(雷鳥 Q3DE PCI音頻加速器)
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP160
封裝: 28 X 28 MM, 3.42 MM HEIGHT, PLASTIC, QFP-160
文件頁數(shù): 49/70頁
文件大?。?/td> 348K
代理商: SAA7780
ThunderBird Q3D PCI Audio
Accelerator
SAA7780
Philips Semiconductors
Product Specification
1999 Sep 30
49
Note: An RC indicates that this bit can be reset to 0 by writing a 1. Writing a zero leaves this bit unchanged.
Revision ID Register - REVISION (RO)
Bit
Name
R/W
Function
15
R_PERR
RC
Received Parity Error: When set to 1, this bit indicates that the SAA7780,
function 1 has detected a PCI bus parity error at least once since this bit was
last reset.
14
S_SERR
RC
Signalled System Error: When set to 1, this bit indicates that the SAA7780,
function 1 has reported a system error on the SERR# signal at least once
since this bit was last reset.
13
SM_ABORT
RO
Signalled Master Abort: The SAA7780, function 1, does not act as a master.
12
RT_ABORT
RO
Received Target Abort: The SAA7780, function 1 does not act as a master.
11
ST_ABORT
RC
Signalled Target Abort: When set to 1, this bit indicates that the SAA7780,
function 1 has signalled a target abort at least once since this bit was last
reset.
10:9
DEVSEL_TM
G
RO
DEVSEL Timing: This field indicates the timing of the DEVSEL output (when
a PCI master is accessing a SAA7780, function 1 resource). It always returns
01 (Bin).
00 = Fast
01 = Medium (Default Timing)
10 = Slow
8
S_PERR
RO
Signalled Parity Error: The SAA7780, function 1, does not act as a bus
master.
7
F_BK2BK
RO
Always returns 1 to indicate support of fast back to back cycles when the
SAA7780, function 1 is the target.
6
UDF
RO
User Definable Features. Always returns 0.
5
MHz66
RO
66 MHz Capable. Always returns 0.
4:0
R
RO
Reserved. These bits always return zero.
PCI CFG 1
D7
D6
D5
D4
D3
D2
D1
D0
Offset 08h
REVISION_ID[7:0]
POR Value
0
0
0
0
0
0
0
0
Bit
Name
R/W
Function
7:0
REVISION_ID
RO
The current revision ID for the SAA7780 joystick.
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