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參數(shù)資料
| 型號(hào)： | SAA7780 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | ThunderBird Q3DE PCI Audio Accelerator(雷鳥 Q3DE PCI音頻加速器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | 28 X 28 MM, 3.42 MM HEIGHT, PLASTIC, QFP-160 |
| 文件頁數(shù)： | 46/70頁 |
| 文件大小： | 348K |
| 代理商： | SAA7780 |
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ThunderBird Q3D PCI Audio
Accelerator
SAA7780
Philips Semiconductors
Product Specification
1999 Sep 30
46
Miscellaneous Configuration Register - MSCCFG (RO/RW)
PCI Configuration Space 1
The following table is a summary of all the PCI configuration space registers. The registers that are block-mates with
the PCI interface (offset 00h - 3Ch) will be detailed following this table. The remainder of the registers will be detailed
with the blocks they control. This register space is for the joystick.
PCI Configuration Space 1 Register Map
PCI CFG 0
D7
D6
D5
D4
D3
D2
D1
D0
Offset 58h
ASYMCLK[1:0]
RDY_EN
CFGCLK
BHEN
PCCH[1:0]
PCPCI
_EN
POR Value
0
0
0
0
0
0
0
0
Bit
Name
R/W
Function
7:6
ASYMCLK
RW
Asymmetrical Clock Select. These bits program the duty cycle for the input
for the two phase DSP clock generator.
5
RDY_EN
RW
Music registers ready enable. When set, the music registers will cause the
PCI interface to retry when either of the music registers (music0 or music1)
are full.
4
CFGCLK
RW
Serial Configuration Port Clock Select. This bit selects the clock output to the
Configuration Serial Port.
0 = Ouput a 400 KHz clock. Incoming data will be synchronized to this clock.
1 = Output the PCI clock.
3
BHEN
RW
Bus Hog Fix Enable.
2:1
PCCH
RW
These two bits are the encoded channel number that the soundblaster will be
on in the PC/PCI mode and are valid only when the PC/PCI mode is enabled.
0
PCPCI_EN
RW
PC/PCI mode enable bit. This bit, when set = 1, will enable the PC/PCI
sideband signals for the Soundblaster legacy mode.
Byte 3
Byte 2
Byte 1
Byte 0
Offset
00h
04h
08h
0Ch
10h
14-2B
2Ch
30-3Bh
3Ch
40-6Bh
6Ch
Device ID
Status
Vendor ID
Command
Class Code
Header Type
Revision ID
Cache Line Size
BIST
Master Latency Timer
GMBASE
Reserved
Subsystem ID
Subsystem Vendor ID
Reserved
Max_Lat
Min_Gnt
Interrupt Pin
Interrupt Line
Reserved
Reserved
Reserved
Reserved
GAMECFG0
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