參數(shù)資料
型號(hào)： SAA7780
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： ThunderBird Q3DE PCI Audio Accelerator(雷鳥 Q3DE PCI音頻加速器)
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP160
封裝： 28 X 28 MM, 3.42 MM HEIGHT, PLASTIC, QFP-160
文件頁數(shù)： 35/70頁
文件大?。?/td> 348K
代理商： SAA7780
ThunderBird Q3D PCI Audio
Accelerator
SAA7780
Philips Semiconductors
Product Specification
1999 Sep 30
35
Note: An RC indicates that this bit can be reset to 0 by writing a 1. Writing a zero leaves this bit unchanged.
POR Value
0
0
0
0
0
0
1
0
D7
D6
D5
D4
D3
D2
D1
D0
F_
BK2BK
UDF
MHz66
R
R
R
R
R
POR Value
1
0
0
0
0
0
0
0
Bit
Name
R/W
Function
15
R_PERR
RC
Received Parity Error: When set to 1, this bit indicates that the SAA7780,
function 0 has detected a PCI bus parity error at least once since this bit was
last reset.
14
S_SERR
RC
Signalled System Error: When set to 1, this bit indicates that the SAA7780,
function 0 has reported a system error on the SERR# signal at least once
since this bit was last reset.
13
SM_ABORT
RC
Signalled Master Abort: When set to 1, this bit indicates that the SAA7780,
function 0 (acting as a master) had to initiate a master abort at least once
since this bit was last reset.
12
RT_ABORT
RC
Received Target Abort: When set to 1, this bit indicates that the SAA7780,
function 0 (acting as a master) has received a target abort at least once since
this bit was last reset.
11
ST_ABORT
RC
Signalled Target Abort: When set to 1, this bit indicates that the SAA7780,
function 0 has signalled a target abort at least once since this bit was last
reset.
10:9
DEVSEL_TM
G
RO
DEVSEL Timing: This field indicates the timing of the DEVSEL output (when
a PCI master is accessing a SAA7780, function 0 resource). It always returns
01 (Bin).
00 = Fast
01 = Medium (Default Timing)
10 = Slow
8
S_PERR
RC
Signalled Parity Error: When set to 1, this bit indicates that the SAA7780,
function 0 was a bus master for a cycle in which PERR# was activated. This
bit cannot be set if the PERR_RESP bit in the command register is not
enabled.
7
F_BK2BK
RO
Always returns 1 to indicate support of fast back to back cycles when the
SAA7780, function 0 is the target.
6
UDF
RO
User Definable Features. Always returns 0.
5
MHz66
RO
66 MHz Capable. Always returns 0.
4:0
R
RO
Reserved. These bits always return zero.
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