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參數(shù)資料
| 型號： | SAA7780 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | ThunderBird Q3DE PCI Audio Accelerator(雷鳥 Q3DE PCI音頻加速器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | 28 X 28 MM, 3.42 MM HEIGHT, PLASTIC, QFP-160 |
| 文件頁數(shù)： | 28/70頁 |
| 文件大?。?/td> | 348K |
| 代理商： | SAA7780 |
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ThunderBird Q3D PCI Audio
Accelerator
SAA7780
Philips Semiconductors
Product Specification
1999 Sep 30
28
BIT Width Device Access Rules
The PCI interface consists of three major blocks, the PCI master interface, the PCI slave interface and the PCI
datapath. The PCI master interface contains the master state machine, the master control logic, and the PM bus
arbiter. The PCI slave interface contains the target state machine, the target control logic and configuration register
headers. The PCI datapath is the de-multiplexing logic for the address, data and byte enable data paths for the PS and
PM busses. The PM and PS busses are described in detail in the SAA7780 Internal Busses section. Partitioning of
these PCI blocks is done in this manner to reduce block inter-connectivity and to provide an interface between the three
major sections of the PCI interface.
PCI Master Interface
The SAA7780 PCI master interface performs the memory read and write cycles initiated by the DMA or Virtual
Registers blocks. The major components of the PCI master interface are the master state machine, the PM bus arbiter
and the master control logic. Each of the functional blocks will be discussed in detail.
PCI Master State Machine
This block performs the handshaking between the PCI interface and the PM internal bus. The PCI master will perform
Device
Cycle Types
Data
Width
Comments
PCI Configuration
Registers
Config Read
Config Write
Any
Follow PCI addressing rules, otherwise assert a target abort.
Note that configuration registers, no matter where they are,
are accessed by configuration cycles only. Note that the PLL
will only allow 8 bit configuration accesses, the Virtual
Registers TBLBASE registers are 32 bit access only, and the
VRCFG is 16 bit access only.
Game Port
I/O Read
I/O Write
8
Any other access will result in a target abort.
AC’97 Codec
I/O Read
I/O Write
16
For PIO type accesses, only 16 bit I/O cycles are allowed,
other wise a target abort will result.
DMA Interface
I/O R/W
Any
Sound Blaster
Registers
I/O Read
I/O Write
8
Any other access will result in a target abort.
Host/DSP Interface
I/O Read
I/O Write
8,16
Word accesses must be word aligned.
Virtual Registers
Mem Read
Any
Follow PCI addressing rules.
Host/DSP Interface
I/O Read
I/O Write
8,16
Usually, only 16 bit accesses will be used to download and
access the DSP. Byte wide are also allowed for DSP
configuration accesses. Word access must be on word
boundaries.
MPU401 Registers
I/O Read
I/O Write
8
Any other access will result in a target abort.
16650 UART
I/O Read
I/O Write
8
Any other access will result in a target abort.
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| SAA7818HL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DVD and CD playback IC |
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