2001 May 30
8
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
DNC13
DNC14
DNC18
DNC15
EXMCLR
CE
V
DDD1
LLC
V
SSD1
LLC2
RES
V
DDD2
V
SSD2
CLKEXT
39
40
41
42
43
44
45
46
47
48
49
50
51
52
N1
N2
P2
N3
P3
N4
C5
P4
D5
N5
P5
C8
D7
N6
NC
I/pu
I/O
I/pd
I/pd
I/pu
P
O
P
O
O
P
P
I
do not connect, reserved for future extensions and for testing
do not connect, reserved for future extensions and for testing
do not connect, reserved for future extensions and for testing
do not connect, reserved for future extensions and for testing
external mode clear (with internal pull-down)
chip enable or reset input (with internal pull-up)
digital supply voltage 1 (peripheral cells)
line-locked system clock output (27 MHz nominal)
digital ground 1 (peripheral cells)
line-locked
1
2
clock output (13.5 MHz nominal)
reset output (active LOW)
digital supply voltage 2 (core)
digital ground 2 (core; substrate connection)
external clock input intended for analog-to-digital conversion of VSB
signals (36 MHz)
MSB of direct analog-to-digital converted output data (VSB)
MSB
1 of direct analog-to-digital converted output data (VSB)
MSB
2 of direct analog-to-digital converted output data (VSB)
MSB
3 of direct analog-to-digital converted output data (VSB)
MSB
4 of direct analog-to-digital converted output data (VSB)
MSB
5 of direct analog-to-digital converted output data (VSB)
digital supply voltage 3 (peripheral cells)
MSB
6 of direct analog-to-digital converted output data (VSB)
MSB
7 of direct analog-to-digital converted output data (VSB)
LSB of direct analog-to-digital converted output data (VSB)
digital ground 3 (peripheral cells)
I
2
C-bus interrupt flag (LOW if any enabled status bit has changed)
digital supply voltage 4 (core)
serial clock input (I
2
C-bus)
digital ground 4 (core)
serial data input/output (I
2
C-bus)
real-time status or sync information, controlled by subaddresses
11H and 12H
real-time status or sync information, controlled by subaddresses
11H and 12H
real-time control output; contains information about actual system clock
frequency, field rate, odd/even sequence, decoder status, subcarrier
frequency and phase and PAL sequence (see document “RTC Functional
Description” available on request); the RTCO pin is enabled via I
2
C-bus
bit RTCE; see notes 5, 6 and Table 35
audio master clock output, up to 50% of crystal clock
ADP8
ADP7
ADP6
ADP5
ADP4
ADP3
V
DDD3
ADP2
ADP1
ADP0
V
SSD3
INT_A
V
DDD4
SCL
V
SSD4
SDA
RTS0
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
P6
M6
L6
N7
P7
L7
C9
M7
P8
N8
D9
P9
C10
N9
D10
P10
M10
O
O
O
O
O
O
P
O
O
O
P
O/od
P
I
P
I/O/od
O
RTS1
70
N10
O
RTCO
71
L10
O/st/pd
AMCLK
72
P11
O
SYMBOL
PIN
TYPE
(1)
DESCRIPTION
QFP160 BGA156