參數(shù)資料
型號: SAA7118H
廠商: NXP SEMICONDUCTORS
元件分類: 顏色信號轉(zhuǎn)換
英文描述: Multistandard video decoder with adaptive comb filter and component video input
中文描述: COLOR SIGNAL DECODER, PQFP160
封裝: 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, MS-022, SOT322-2 , QFP-160
文件頁數(shù): 157/169頁
文件大?。?/td> 665K
代理商: SAA7118H
2001 May 30
157
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
Table 137
Vertical chrominance phase offset ‘00’; register set A [B8H[7:0]] and B [E8H[7:0]]
Table 138
Vertical luminance phase offset ‘00’; register set A [BCH[7:0]] and B [ECH[7:0]]
16 PROGRAMMING START SET-UP
16.1
Decoder part
The given values force the following behaviour of the SAA7118 decoder part:
The analog input AI11 expects an NTSC M, PAL B, D, G, H and I or SECAM signal in CVBS format; analog anti-alias
filter and AGC active
Automatic field detection enabled
Standard ITU 656 output format enabled on expansion (X) port
Contrast, brightness and saturation control in accordance with ITU standards
Adaptive comb filter for luminance and chrominance activated
Pins LLC, LLC2, XTOUT, RTS0, RTS1 and RTCO are set to 3-state.
Table 139
Decoder part start set-up values for the three main standards
VERTICAL CHROMINANCE PHASE
OFFSET
CONTROL BITS D7 TO D0
YPC07
YPC06
YPC05
YPC04
YPC03
YPC02
YPC01
YPC00
Offset = 0
Offset =
32
32
= 1 line
Offset =
255
32
lines
0
0
1
0
0
1
0
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
VERTICAL LUMINANCE PHASE
OFFSET
CONTROL BITS D7 TO D0
YPY07
YPY06
YPY05
YPY04
YPY03
YPY02
YPY01
YPY00
Offset = 0
Offset =
32
32
= 1 line
Offset =
255
32
lines
0
0
1
0
0
1
0
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
SUB
ADDRESS
(HEX)
REGISTER
FUNCTION
BIT NAME
(1)
VALUES (HEX)
NTSC M
PAL B, D,
G, H AND I
SECAM
00
01
chip version
increment delay
ID7 to ID4
X, WPOFF, GUDL1, GUDL0 and
IDEL3 to IDEL0
FUSE1, FUSE0 and MODE5 to MODE0
X, HLNRS, VBSL, CPOFF, HOLDG,
GAFIX, GAI28 and GAI18
GAI17 to GAI10
GAI27 to GAI20
HSB7 to HSB0
HSS7 to HSS0
AUFD, FSEL, FOET, HTC1, HTC0,
HPLL, VNOI1 and VNOI0
read only
47
47
47
02
03
analog input control 1
analog input control 2
C0
10
C0
10
C0
10
04
05
06
07
08
analog input control 3
analog input control 4
horizontal sync start
horizontal sync stop
sync control
90
90
EB
E0
98
90
90
EB
E0
98
90
90
EB
E0
98
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