參數資料
型號: SAA7118H
廠商: NXP SEMICONDUCTORS
元件分類: 顏色信號轉換
英文描述: Multistandard video decoder with adaptive comb filter and component video input
中文描述: COLOR SIGNAL DECODER, PQFP160
封裝: 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, MS-022, SOT322-2 , QFP-160
文件頁數: 36/169頁
文件大?。?/td> 665K
代理商: SAA7118H
2001 May 30
36
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
8.1.4
C
LOCK GENERATION CIRCUIT
The internal CGC generates all clock signals required for
the video input processor.
The internal signal LFCO is a digital-to-analog converted
signal provided by the horizontal PLL. It is the multiple of
the line frequency:
6.75 MHz = 429
×
f
H
(50 Hz), or
6.75 MHz = 432
×
f
H
(60 Hz).
The LFCO signal is multiplied by a factor of 2 and 4 in the
internalPLLcircuit(includingphasedetector,loopfiltering,
VCO and frequency divider) to obtain the output clock
signals. The rectangular output clocks have a 50% duty
factor.
Table 3
Decoder clock frequencies
CLOCK
FREQUENCY (MHz)
XTALO
LLC
LLC2
LLC4 (internal)
LLC8 (virtual)
24.576 or 32.110
27
13.5
6.75
3.375
Fig.21 Block diagram of the clock generation circuit.
BAND PASS
FC = LLC/4
ZERO
CROSS
DETECTION
PHASE
DETECTION
LOOP
FILTER
DIVIDER
1/2
DIVIDER
1/2
OSCILLATOR
MHB330
LLC2
LLC
LFCO
8.1.5
P
OWER
-
ON RESET AND
C
HIP
E
NABLE
(CE)
INPUT
A missing clock, insufficient digital or analog V
DDA0
supply voltages (below 2.8 V) will start the reset sequence; all outputs
are forced to 3-state (see Fig.22). The indicator output RES is LOW for approximately 128 LLC after the internal reset
and can be applied to reset other circuits of the digital TV system.
It is possible to force a reset by pulling the Chip Enable pin (CE) to ground. After the rising edge of CE and sufficient
power supply voltage, the outputs LLC, LLC2 and SDA return from 3-state to active, while the other signals have to be
activated via programming.
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