參數(shù)資料
型號: SAA7118H
廠商: NXP SEMICONDUCTORS
元件分類: 顏色信號轉(zhuǎn)換
英文描述: Multistandard video decoder with adaptive comb filter and component video input
中文描述: COLOR SIGNAL DECODER, PQFP160
封裝: 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, MS-022, SOT322-2 , QFP-160
文件頁數(shù): 142/169頁
文件大?。?/td> 665K
代理商: SAA7118H
2001 May 30
142
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
Table 93
Global control 1; global set 80H[3:0]
X = don’t care.
Note
1.
Although the ICLKO I/O is independent of ICKS2 and ICKS3, this selection can only be used if ICKS2 = 1.
15.7.2
S
UBADDRESSES
83H
TO
87H
Table 94
X-port I/O enable and output clock phase control; global set 83H[5:4]
Table 95
X-port I/O enable and output clock phase control; global set 83H[2:0]
X = don’t care.
I-PORT AND SCALER BACK-END CLOCK SELECTION
CONTROL BITS D3 TO D0
ICKS3
ICKS2
ICKS1
ICKS0
ICLK output and back-end clock is line-locked clock LLC from decoder
ICLK output and back-end clock is XCLK from X-port
ICLK output is LLC and back-end clock is LLC2 clock
Back-end clock is the ICLK input
IDQ pin carries the data qualifier
IDQ pin carries a gated back-end clock (DQ AND CLK)
IDQ generation only for valid data
IDQ qualifies valid data inside the scaling region and all data outside the scaling
region
X
X
X
X
X
X
0
1
X
X
0
0
1
1
X
X
X
X
0
1
0
1
X
X
X
X
X
(1)
X
0
1
X
X
OUTPUT CLOCK PHASE CONTROL
CONTROL BITS D5 AND D4
XPCK1
XPCK0
XCLK default output phase, recommended value
XCLK output inverted
XCLK phase shifted by approximately 3 ns
XCLK output inverted and shifted by approximately 3 ns
0
0
1
1
0
1
0
1
X-PORT I/O ENABLE
CONTROL BITS D2 TO D0
XRQT
XPE1
XPE0
X-port output is disabled by software
X-port output is enabled by software
X-port output is enabled by pin XTRI at logic 0
X-port output is enabled by pin XTRI at logic 1
XRDY output signal is A/B task flag from event handler (A = 1)
XRDY output signal is ready signal from scaler path (XRDY = 1 means the
SAA7118 is ready to receive data)
X
X
X
X
0
1
0
0
1
1
X
X
0
1
0
1
X
X
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