參數(shù)資料
型號: SAA7118H
廠商: NXP SEMICONDUCTORS
元件分類: 顏色信號轉(zhuǎn)換
英文描述: Multistandard video decoder with adaptive comb filter and component video input
中文描述: COLOR SIGNAL DECODER, PQFP160
封裝: 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, MS-022, SOT322-2 , QFP-160
文件頁數(shù): 148/169頁
文件大小: 665K
代理商: SAA7118H
2001 May 30
148
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive
comb filter and component video input
SAA7118
Table 110
Task handling control; register set A [90H[2:0]] and B [C0H[2:0]]
X = don’t care.
15.7.6
S
UBADDRESSES
91H
TO
93H
Table 111
X-port formats and configuration; register set A [91H[7:3]] and B [C1H[7:3]]
X = don’t care.
EVENT HANDLER CONTROL
CONTROL BITS D2 TO D0
RPTSK
STRC1
STRC0
Event handler triggers immediately after finishing a task
Event handler triggers with next V-sync
Event handler triggers with field ID = 0
Event handler triggers with field ID = 1
If active task is finished, handling is taken over by the next task
Active task is repeated once, before handling is taken over by the next task
X
X
X
X
0
1
0
0
1
1
X
X
0
1
0
1
X
X
SCALER INPUT FORMAT AND CONFIGURATION SOURCE
SELECTION
CONTROL BITS D7 TO D3
CONLV
HLDFV
SCSRC1 SCSRC0
SCRQE
Only if XRQT[83H[2]] = 1: scaler input source reacts on
SAA7118 request
Scaler input source is a continuous data stream, which cannot
be interrupted (must be logic 1, if SAA7118 decoder part is
source of scaler or XRQT[83H[2]] = 0)
Scaler input source is data from decoder, data type is
provided according to Table 15
Scaler input source is Y-C
B
-C
R
data from X-port
Scaler input source is raw digital CVBS from selected analog
channel, for backward compatibility only, further use is not
recommended
Scaler input source is raw digital CVBS (or 16-bit Y + C
B
-C
R
, if
no 16-bit outputs are active) from X-port
SAV/EAV code bits D6 and D5 (F and V) may change
between SAV and EAV
SAV/EAV code bits D6 and D5 (F and V) are synchronized to
scalers output line start
SAV/EAV code bit D5 (V) and V-gate on pin IGPV as
generated by the internal processing; see Fig.43
SAV/EAV code bit D5 (V) and V-gate are inverted
X
X
X
X
0
X
X
X
X
1
X
X
0
0
X
X
X
X
X
0
1
1
0
X
X
X
X
1
1
X
X
0
X
X
X
X
1
X
X
X
0
X
X
X
X
1
X
X
X
X
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