參數(shù)資料
型號(hào)： SAA6750H
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： Encoder for MPEG2 image recording EMPIRE
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP208
封裝： PLASTIC, SQFP-208
文件頁(yè)數(shù)： 41/60頁(yè)
文件大?。?/td> 217K
代理商： SAA6750H
2000 May 03
41
Philips Semiconductors
Product specification
Encoder for MPEG2 image recording
(EMPIRE)
SAA6750H
Table 24
Example for control register settings
REGISTER BYTE
DATA BYTE
INTER/INTRA MODE
INTRA FORCE MODE
BINARY
HEX
BINARY
HEX
Control
PMI
WR
RD
BUF
RFR
MC
ML
FIDP and vertical shift bottom
VREFP and vertical shift top
HREFP and horizontal shift
Filter coefficient a3
Filter coefficient a2
Filter coefficient a1
Shift start
BS_BUFFER lower level
BS_BUFFER upper level (LSB)
BS_BUFFER upper level (MSB)
Bus address (LSB)
Bus address (MSB)
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1000 1000
0010 0011
1000 0100
0110 1011
0000 0111
0000 0001
1010 0001
1001 0111
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 1000
0000 0000
1111 1111
0100 1111
1111 1111
1111 1111
88
23
84
6B
07
01
A1
97
00
00
00
00
00
00
08
00
FF
4F
FF
FF
1010 1000
0010 0011
1000 0100
1000 0001
0000 0111
0000 0001
1010 0001
1001 0111
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0100
0000 0000
1111 1111
0100 1111
1111 1111
1111 1111
A8
23
84
81
07
01
A1
97
00
00
00
00
00
00
04
00
FF
4F
FF
FF
7.10
DRAM interface
7.10.1
G
ENERAL
The DRAM interface of the SAA6750H schedules and
handles all accesses of internal read and write clients to
the external 4
×
4 Mbit DRAM memory. It also takes care
of the DRAM refresh after Power-on reset and performs
the initialization of the external DRAM.
Four fast page mode or Extended Data Out (EDO) DRAM
devices (t
RAC
= 60 ns) with 16-bit data and 9-bit row and
column address have to be applied in parallel. Therefore
the accessible DRAM format is 262144
×
64 bits.
7.10.2
A
PPLICATION HINTS
It should be noted that the DRAM interface is timing
sensitive. Make sure that wires between the SAA6750H
and the external DRAM memories are as short as
possible. In addition the CASN, RASN, address and data
lines should have approximately the same parasitic load.
7.10.3
F
UNCTIONAL DESCRIPTION
7.10.3.1
Interface definition
The connection between the DRAM interface and the
memoryconsistsof77 signals.ADR0 to ADR8areusedto
transfer the row or the column address. The signals CASN
and RASN indicate, that a column/row address is present
on ADR0 to ADR8. WEN enables a write access and OEN
selects/deselects the associated memory chip.
The signals CASN, RASN, WEN and OEN are
active LOW.
7.10.3.2
DRAM initialization
After the external reset signal RESETN becomes inactive,
the DRAM interface immediately starts generating a
DRAM initialization sequence. First, the Row Address
Strobe (RASN) and Column Address Strobe (CASN) are
kept stable in HIGH state for a minimum of 200
μ
s. After
this the DRAM interface generates a sequence of
initialization pulses. This sequence consists of 9 CASN
cycles before RASN refresh (CBR) events (see Fig.15).
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