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參數(shù)資料
| 型號(hào)： | SAA6750H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Encoder for MPEG2 image recording EMPIRE |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 封裝： | PLASTIC, SQFP-208 |
| 文件頁數(shù)： | 28/60頁 |
| 文件大?。?/td> | 217K |
| 代理商： | SAA6750H |
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2000 May 03
28
Philips Semiconductors
Product specification
Encoder for MPEG2 image recording
(EMPIRE)
SAA6750H
7.6
Data output port
7.6.1
G
ENERAL
The data output port connects the data output stream of
the SAA6750H to the outside world. The data output port
interface implements a Motorola-style bus protocol with
different addressing modes. The status of the internal data
buffer is reported by dedicated output signals.
The data output interface of the SAA6750H will always
behave as a slave on the bus.
7.6.2
D
ATA OUTPUT FORMAT
The output data is provided in 16-bit words. The most
significant bit of the data word represents the first bit in the
serial MPEG2 elementary stream. Depending on the
addressing mode the external host uses the bus transfers
plain data (non-multiplex mode) or a multiplex of
addresses and data (multiplex mode) for selection of the
data output port, See Section 7.6.3 for information about
the interface protocol.
7.6.3
F
UNCTIONAL DESCRIPTION
7.6.3.1
General
The data output port supports Motorola-style bus protocol.
The addressing can be carried out by the external host in
two different modes:
1.
Internal address decoding
Thedataoutputportprovidesaprogrammableinternal
address decoding. This does support e.g. the use of
several slaves on the bus. The data output port’s
16-bit address is determined by the setting of bytes
Bus address (MSB) and Bus address (LSB) in the
I
2
C-bus control register (see Table 21). During reset
mode the contents of Bus address will be set to
0000H.
The external host may select the data output port by
sending the address value that was programmed in
the I
2
C-bus control register. In internal address
decoding mode, the output data bus carries
multiplexed address and data information.
Pin CSN is not used in this mode and must be set to
HIGH.
External address decoding
External address decoding mode may be appropriate
if e.g. an external address decoding hardware is
available or if the SAA6750H is the only slave on the
bus. The data output port is selected by setting
pin CSN to LOW. In this mode, the internal address
decoder is disabled and consequently the setting of
bytes Bus address is ignored. In external address
decoding mode, the output data bus carries plain data
information.
2.
The bus protocol mode and address decoding mode are
depending on the setting of the I
2
C-bus control register
bit BUS. See Tables 12 and 22 and Section 7.6.3.4 for
detailed information.
Table 12
Data output port mode selection
Notes
1.
2.
Bit BUS is set to logic 0 during reset mode.
The 16-bit data output port address (see Table 21) must be loaded via the I
2
C-bus with the application specific value.
The default address is set to 0000H during reset mode.
X = don’t care.
3.
BIT BUS
PIN I_MN
FUNCTION
0
LOW
Motorola-style protocol mode with external address decoding (non-multiplexed bus);
note 1
Motorola-style protocol mode with internal 16-bit address decoding (multiplexed bus);
notes 1 and 2
reserved
1
LOW
X
(3)
HIGH
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| SAA6752HS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer |
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