參數(shù)資料
型號: SAA6750H
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: Encoder for MPEG2 image recording EMPIRE
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP208
封裝: PLASTIC, SQFP-208
文件頁數(shù): 34/60頁
文件大小: 217K
代理商: SAA6750H
2000 May 03
34
Philips Semiconductors
Product specification
Encoder for MPEG2 image recording
(EMPIRE)
SAA6750H
7.9.4.2
I
2
C-bus data transfer to subaddresses
The following tables describe the data transfer to or from the subaddresses 0 to 7. See Sections 7.9.3.2, 7.9.3.3
and 7.9.3.4 for information of the data transfer modes.
Table 20
Data transfer to subaddresses
7.9.4.3
Quantization matrix SRAM
SRAM memory containing a constant table for the macroblock processor quantization function.
The data to be loaded into this memory will be part of the application software and described in the software specification.
Remark
: Data may only be sent to this subaddress if the SAA6750H is in the init mode (see Table 23).
7.9.4.4
Microcode SRAM
SRAM memory containing the ASIP’s microcode.
The microcode to be loaded into this memory will be part of the application software and described in the software
specification.
Remark
: Data may only be sent to this subaddress if the SAA6750H is in the init mode (see Table 23).
SUBADDRESS
(HEX)
STORAGE
NAME
DATA
TRANSFER
MODE
ADDRESS
BYTES PER
TRANSMISSION
DATA BYTES
PER
TRANSMISSION
I
2
C-BUS BYTE
TRANSFERS PER
TRANSMISSION
00
quantization
matrix SRAM
microcode
SRAM
microcode
ROM table
microcode
constants
serial output
register
serial input
register
control bits
register
internal use
randomaccess
write mode
randomaccess
write mode
randomaccess
write mode
randomaccess
write mode
read mode
1
1
4 = 2 + 1 + 1
01
2
23
27 = 2 + 2 + 23
02
2
3
7 = 2 + 2 + 3
03
1
3
6 = 2 + 1 + 3
04
0
21
24 = 2 + 1 + 21
05
randomaccess
write mode
write mode
1
24
6 = 2 + 1 + 3
06
0
20
22 = 2 + 20
07
none
SUBADDRESS
(HEX)
STORAGE NAME
DESIGN BLOCK
DEPTH
(WORDS)
WIDTH
(BITS)
DATA TRANSFER MODE
00
quantization matrix SRAM
MBP
128
8
random access write mode
SUBADDRESS
(HEX)
STORAGE NAME
DESIGN BLOCK
DEPTH
(WORDS)
WIDTH
(BITS)
DATA TRANSFER MODE
01
microcode SRAM
ASIP
1024
177
random access write mode
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