參數(shù)資料
型號： SAA6750H
廠商： NXP SEMICONDUCTORS
元件分類： 消費家電
英文描述： Encoder for MPEG2 image recording EMPIRE
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP208
封裝： PLASTIC, SQFP-208
文件頁數(shù)： 30/60頁
文件大?。?/td> 217K
代理商： SAA6750H
2000 May 03
30
Philips Semiconductors
Product specification
Encoder for MPEG2 image recording
(EMPIRE)
SAA6750H
7.6.3.4
Motorola-style protocol mode
1.
Internal address decoding
The host starts a data transfer cycle by applying the
data output port address onto the multiplexed
address/data lines (see Fig.16). By setting AS_ALE to
LOWthehostindicatesthattheaddressisvalidandby
setting DS_RDN to LOW that it gives up driving the
address data and allows the data output interface of
the SAA6750H to send data via the bus. The
SAA6750H will drive DTACK_RDY to LOW, when it
has placed valid data onto AD15 to AD0.
A DS_RDN = HIGH by the host will force the
SAA6750H to set DTACK_RDY back to HIGH, to stop
driving the data bus and to interrupt the transfer of the
current word, however, this may lead to a loss of data.
The data read sequence may be repeated by setting
DS_RDN to LOW and so forth.
The transfer cycle is ended as soon as the host sets
DS_RDN and AS_ALE back to HIGH. After this, the
SAA6750H will also set DTACK_RDY to HIGH and
stops driving data after a delay t
dz
(see Chapter “Characteristics”). A new transfer cycle
may not be started as long as DTACK_RDY is LOW or
the SAA6750H is driving the data bus. CSN has to be
HIGH all the time. See Fig.16 and
Chapter “Characteristics” for timing information.
External address decoding
The host starts a data transfer cycle by setting the
CSN signal to LOW (see Fig.17). By setting DS_RDN
to LOW the host indicates that it wants to read a data
word and allows the data output interface of the
SAA6750H to send data via the bus. The SAA6750H
will drive DTACK_RDY to LOW, when it has placed
valid data onto AD15 to AD0. A DS_RDN = HIGH by
the host will force the SAA6750H to set DTACK_RDY
back to HIGH, to stop driving the data bus and to
interrupt the transfer of the current word however this
may lead to a loss of data. The data read sequence
may be repeated by setting DS_RDN to LOW and so
forth.
The transfer cycle is ended as soon as the host sets
DS_RDN and CSN back to HIGH. After this, the
SAA6750H will also set DTACK_RDY to HIGH and
stop driving data after a delay t
dz
(see Chapter “Characteristics”). A new transfer cycle
may not be started as long as DTACK_RDY is LOW or
the SAA6750H is driving the data bus. AS_ALE has to
be HIGH all the time. See Fig.17 and
Chapter “Characteristics” for timing information.
2.
7.7
Application Specific Instruction-set Processor
(ASIP)
7.7.1
G
ENERAL
The ASIP is a programmable controller specially designed
for the architecture and system requirements of the
SAA6750H. Generally it has to cover internal control
functions. The following tasks are handled:
Controlling of the MBP
Macroblock base address generation for the MBP
Motion vector generation
Bitstream header generation
Management of bitstream assembly
Bit-rate control.
The microcode of the ASIP has to be downloaded by the
I
2
C-bus into internal RAMs during initialization of the
SAA6750H.
The ASIP is able to communicate with the outside world
via an I
2
C-bus interface (see Section 7.9.4).
7.8
Global controller
7.8.1
G
ENERAL
The global controller generates a global scheduling for the
loosely coupled processes of the SAA6750H. It is
controlled by the bits E_ST, E_SP, SS and STD which are
located in the I
2
C-bus control register (see Table 22). The
global controller is automatically synchronized with the
front-end block.
7.9
I
2
C-bus interface and controller
7.9.1
G
ENERAL
The I
2
C-bus interface within the SAA6750H is a slave
transceiver. It is used to download the microcode of the
ASIP, constants and tables as well as the quantization
matrix table to the MBP. In addition, all control settings are
carried out via the I
2
C-bus. The read mode may be used to
read back data from registers connected internally to the
ASIP. In total 8 subaddresses are used to store or read
data.
The I
2
C-bus interface is compliant to the I
2
C-bus standard
at 100 and 400 kHz clock frequency and suitable for
bus-line voltage levels from 3.3 to 5 V.
The I
2
C-bus slave address (SAD) is 40H respectively 42H
depending on the state of pin MAD. This allows the use of
two devices SAA6750H in one application. See the
general I
2
C-bus specification for detailed information on
the bus protocol.
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