參數(shù)資料
型號: SAA6750H
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: Encoder for MPEG2 image recording EMPIRE
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP208
封裝: PLASTIC, SQFP-208
文件頁數(shù): 39/60頁
文件大?。?/td> 217K
代理商: SAA6750H
2000 May 03
39
Philips Semiconductors
Product specification
Encoder for MPEG2 image recording
(EMPIRE)
SAA6750H
Notes
1.
Changes of this setting are only allowed in init mode or soft reset mode. See Section 7.2.3 for information of the
SAA6750H operating modes.
The range of sensible values is 00H to 10H for PAL and 00H to 07H for NTSC.
2.
48 to 4E
VST0 to
VST6
(1)
VREFP
(1)
vertical shift top field
10
value determines number of H-syncs occurring after V-sync
before the top field line based processing starts; note 2
VSYNC signal polarity selection; LOW: VSYNC signal not
inverted, VREF signal expected at pin VSYNC;
HIGH: VSYNC signal inverted, vertical blanking qualifier
expected at VSYNC pin; this setting does not affect the sync
derived from SAV and EAV codes
setting determines the number of clock cycles occurring after
the H-sync before the line based processing starts; value
should have a multiple of 4 because a minimum data
sequence (C
B
, Y, C
R
and Y) needs 4 clock cycles
HSYNC signal polarity selection; LOW: HSYNC signal not
inverted, HREF signal expected at pin HSYNC;
HIGH: HSYNC signal inverted, horizontal blanking qualifier
expected at pin HSYNC; this setting does not affect the sync
derived from SAV and EAV codes
filter coefficient a3 for the horizontal filtering of video input
signal
filter coefficient a2 for the horizontal filtering of video input
signal
filter coefficient a1 for the horizontal filtering of video input
signal
use default setting given in the software specification
4F
55 to 56
HOR0 to
HOR6
(1)
horizontal shift
9
57
HREFP
(1)
58 to 5F
FA30 to
FA37
FA20 to
FA27
FA10 to
FA17
SH0 to
SH7
BL0 to
BL5
BU0 to
BU7
Filter coefficient a3
8
60 to 67
Filter coefficient a2
7
68 to 6F
Filter coefficient a1
6
70 to 77
Shift start (time slot)
5
78 to 7D
BS_BUFFER lower
level
4
lower watermark value for data output buffer monitoring in
64-bit steps
not used; it must be set to LOW during initialization
upper watermark value for data output buffer monitoring
(LSB); the valid range for BS_BUFFER upper level is
1 to 32752 in 128-bit steps
upper watermark value for data output buffer monitoring
(MSB); the valid range for BS_BUFFER upper level is
1 to 32752 in 128-bit steps
not used; it must be set to LOW during initialization
address value for internal address decoding mode of data
output port (LSB)
7E to 7F
80 to 87
BS_BUFFER upper
level (LSB)
3
88 to 8E
BU8 to
BU14
BS_BUFFER upper
level (MSB)
2
8F
90 to 97
DADR0
to
DADR7
DADR8
to
DADR15
Bus address (LSB)
1
98 to 9F
Bus address (MSB)
0
address value for internal address decoding mode of data
output port (MSB)
BIT
ADDRESS
(HEX)
BIT
NAME
CONTROL WORD
NAME
DATA
BYTE
DESCRIPTION
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