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參數資料
| 型號： | SAA6750H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Encoder for MPEG2 image recording EMPIRE |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 封裝： | PLASTIC, SQFP-208 |
| 文件頁數： | 31/60頁 |
| 文件大?。?/td> | 217K |
| 代理商： | SAA6750H |
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2000 May 03
31
Philips Semiconductors
Product specification
Encoder for MPEG2 image recording
(EMPIRE)
SAA6750H
7.9.2
S
PECIAL CONSIDERATIONS
Eight subaddresses are used to read or write data from or
to the internal SRAM memories and registers of the
SAA6750H. An explanation of purpose, function and data
transfer will be given in the following chapters. It should be
noted that all subaddresses can only be used as data sink
or as data source. It is not possible to write data into a
register and read it back later on.
Due to the internal memory architecture data may only be
transmitted to the subaddresses 00H to 03H when the
SAA6750H is in init mode. After the control bit E_ST is set
to logic 1, sending data via the I
2
C-bus to the SRAMs
00H to 03H is forbidden.
The I
2
C-bus interface will not respond to the general call
address 00H and it will not use clock stretch to slow down
a data transmission.
The acknowledgement of a data byte by the I
2
C-bus
interface only indicates that the transmission was received
and that the correct slave address was used. It does not
necessarily say that the data reached its destination.
E.g. also if a subaddress outside the valid range from 00H
to 007H was sent to the SAA6750H or a transmission to
subaddress 01H took place while bit E_ST was logic 1, the
I
2
C-bus interface will return an acknowledge.
A special sequence of commands is used to read data
from the subaddress 04H. See Section 7.9.3.4 for detailed
information.
7.9.3
I
2
C-
BUS DATA TRANSFER MODES
7.9.3.1
General
Data transfer follows the I
2
C-bus specification for fast
(400 kHz) or normal (100 kHz) mode. The SAA6750H
slave address in write mode is:
40H if pin MAD is LOW
42H if pin MAD is HIGH.
For read operations the following slave addresses have to
be used:
41H if pin MAD is LOW
43H if pin MAD is HIGH.
The I
2
C-bus will transfer data always as a whole byte
consisting of 8 bits. If the address or data word consists of
several bytes, the Most Significant Byte (MSB) has to be
sent first and the Least Significant Byte (LSB) last. This
rule does also apply for read operations. In this case the
MSB will be received first.
If the memory’s address or data word does not have a
width of a multiple of 8 bits, dummy bits have to be added
on the left side (most significant bit side) of the MSB.
E.g. the ASIP microcode has 177 bits wide data words.
177 divided by 8 gives 22 and a remainder of 1. Therefore
the I
2
C-bus master has to send 23 data bytes of which the
higher 7 bits of the MSB are dummy bits. Also the same
rule applies for read operations.
Depending on the type of storage the data transfer to or
from the memories and registers has to be carried out in
different modes which will be described in the following
chapters.
Table 15
Abbreviations used in data transfer diagrams
ABBREVIATION
FUNCTION
S
I
2
C-bus START condition,
generated by master
I
2
C-bus REPEATED START
condition, generated by master
Higher 7 bits of slave address byte:
7-bit slave address: 0100000
(pin MAD = LOW), 40H/41H;
7-bit slave address: 0100001
(pin MAD = HIGH), 42H/43H
write mode: LSB of slave address
byte = 0
read mode: LSB of slave address
byte = 1
master acknowledge (acknowledge
generated by master)
master acknowledge not
(no acknowledge by master)
slave acknowledge (acknowledge
generated by SAA6750H)
8-bit subaddress
address byte
data byte to be written/read
I
2
C-bus STOP condition, generated
by master
RS
SAD
W
R
MA
MN
SA
SD
ADR
DATA
P
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