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參數(shù)資料
| 型號(hào)： | SAA4978 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Picture Improved Combined Network PICNIC |
| 中文描述： | 圖片改進(jìn)聯(lián)合網(wǎng)絡(luò)野餐 |
| 文件頁數(shù)： | 41/56頁 |
| 文件大小： | 296K |
| 代理商： | SAA4978 |
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1999 May 03
41
Philips Semiconductors
Product specification
Picture Improved Combined Network
(PICNIC)
SAA4978H
Oscillator stage (operation with crystal or external clock)
f
osc
C
L34
C
L35
R
ser1(xtal)
C
par(xtal)
oscillator frequency
recommended load
capacitor
12
12
18
250
7
MHz
pF
pF
pF
see Fig.11
crystal series resistance
crystal parallel
capacitance
see Fig.12
see Fig.12
I
2
C-bus signal: SDA and SCL;
note 8
V
IH
V
IL
V
OL
f
SCL
t
HD;STA
t
SCLL
t
SCLH
t
SU;DAT
t
SU;DAT1
HIGH-level input voltage
LOW-level input voltage
LOW-level output voltage
SCL clock frequency
hold time START condition
SCL LOW time
SCL HIGH time
data set-up time
data set-up time (before
repeated START
condition)
data set-up time (before
STOP condition)
set-up time repeated
START
set-up time STOP
condition
0.7V
DDIO
0.6
1.3
0.6
100
0.6
0.3V
DDIO
0.4
400
V
V
V
kHz
μ
s
μ
s
μ
s
ns
μ
s
I
OL
= 3.0 mA
t
SU;DAT2
0.6
μ
s
t
SU;STA
0.6
μ
s
t
SU;STO
0.6
μ
s
SNERT bus timing valid for both 1 and 2 Mbaud: SNDA and SNCL;
see Fig.10
V
OH
V
OL
V
IL
V
IH
t
su(i)(SNCL)
t
h(i)(SNCL)
t
h(o)
t
su(o)
t
dis(o)
t
cy(SNCL)
t
SNRSTH
t
d(SNRST-DAT)
HIGH-level output voltage
LOW-level output voltage
LOW-level input voltage
HIGH-level input voltage
input set-up time to SNCL
input hold time to SNCL
output hold time
output set-up time
output disable time
SNCL cycle time
SNRST pulse HIGH time
delay SNRST pulse to
data
I
OH
=
0.06 mA
I
OL
= 1.6 mA
2.4
0
2.0
80
0
50
260
500
500
200
0.4
0.8
5.5
200
1000
V
V
V
V
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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| SAA4981T | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Monolithic integrated 16 : 9 compressor |
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