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參數(shù)資料
| 型號(hào)： | SAA4978 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Picture Improved Combined Network PICNIC |
| 中文描述： | 圖片改進(jìn)聯(lián)合網(wǎng)絡(luò)野餐 |
| 文件頁數(shù)： | 10/56頁 |
| 文件大?。?/td> | 296K |
| 代理商： | SAA4978 |
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1999 May 03
10
Philips Semiconductors
Product specification
Picture Improved Combined Network
(PICNIC)
SAA4978H
Fig.3 Pin configuration.
handbook, halfpage
SAA4978H
1
1
1
4
8
40
120
81
MHB174
7
FUNCTIONAL DESCRIPTION
The SAA4978H consists of the following main functional
blocks:
Analog preprocessing and analog-to-digital conversion
Digital processing at 1f
H
level
Digital processing at 2f
H
level
Digital-to-analog conversion
Line-locked clock generation
Crystal oscillator
Control interfacing I
2
C-bus and SNERT
Register I/O
Programmable Signal Positioner (PSP)
80C51 microcontroller core
Board level testability provisions.
7.1
Analog input blocks
7.1.1
G
AIN ELEMENTS FOR AUTOMATIC GAIN CONTROL
(9 dB
RANGE
)
A variable amplifier is used to map the possible YUV input
range to the analog-to-digital converter range e.g. as
defined for SCART signals.
According to this specification, a lift of 6 dB up to a drop of
3 dB may be necessary with respect to the nominal values.
The gain setting within the required minimum 9 dB range
is performed digitally via the internal microcontroller.
For this purpose a gain setting digital-to-analog converter
is incorporated. The smallest step in the gain setting
should be hardly visible on the picture, this can be met with
smaller steps of 0.4%/step.
Luminance and chrominance gain settings can be
separately controlled. The reason for this split is that
U and V may have already been gain adjusted by an
Automatic Chrominance Control (ACC), whereas
luminance is to be adjusted by the SAA4978H AGC.
However, for RGB originated sources, Y, U and V should
be adjusted with the same AGC gain.
7.1.2
C
LAMP CIRCUIT
,
CLAMPING
Y
TO DIGITAL LEVEL
32
AND
UV
TO
0 (
TWOS COMPLEMENT
)
A clamp circuit is applied to each input channel, to map the
colourless black level in each video line (on the sync back
porch) to level 32 at 9 bits for Y and to the centre level of
the converters for U and V. During the clamp period, an
internally generated clamp pulse is used to switch-on the
clamp action.
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PDF描述 |
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| SAA4978H | Picture Improved Combined Network PICNIC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA4978H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Picture Improved Combined Network PICNIC |
| SAA4979H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Sample rate converter with embedded high quality dynamic noise reduction and expansion port |
| SAA4981 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Monolithic integrated 16 : 9 compressor |
| SAA4981T | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Monolithic integrated 16 : 9 compressor |
| SAA4990 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Progressive scan-Zoom and Noise reduction IC PROZONIC |
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