參數(shù)資料
型號(hào)： SAA4978
廠商： NXP Semiconductors N.V.
英文描述： Picture Improved Combined Network PICNIC
中文描述： 圖片改進(jìn)聯(lián)合網(wǎng)絡(luò)野餐
文件頁(yè)數(shù)： 11/56頁(yè)
文件大小： 296K
代理商： SAA4978
1999 May 03
11
Philips Semiconductors
Product specification
Picture Improved Combined Network
(PICNIC)
SAA4978H
A voltage controlled current source construction, which
references to voltage reference points in the ladders of the
analog-to-digital converters, provides a current on the
input of the YUV signals in order to bring the signals to the
correct DC value. This current is proportional to the DC
error, but is limited to
±
150
μ
A. It is essential that the clamp
current becomes zero with a zero error and that the
asymmetry between positive and negative clamp currents
is limited to within 10%. When the clamping action is off,
the residual clamp current should be very low, so that the
clamp level will not drift away within a video line.
The clamp level in the Y channel has a minimum value of
600 mV to ensure undisturbed clamping for maximum
Y input signals with top sync levels up to 600 mV. In order
to improve common mode rejection it is recommended to
connect the same source impedance as used in the YIN
input at the DIFFIN input to ground.
7.1.3
A
NALOG ANTI
-
ALIASING PREFILTER
A 3rd-order linear phase filter is applied to each of the
Y, U and V channels. It provides a notch on f
clk
(16 MHz
at Y, U and V) to strongly prevent aliasing to low
frequencies, which would be the most disturbing.
The bandwidth of the filters is designed for
3 dB at
5.6 MHz. The filters can be bypassed if external filtering
with other characteristics is desired. In the bypass mode
the gain accuracy of the front-end part is 4% instead of 8%
for the filter-on mode.
7.1.4
9-
BIT ANALOG
-
TO
-
DIGITAL CONVERSION
Three identical multi-step type analog-to-digital converters
are used to convert the Y, U and V inputs with a 16 MHz
data rate. The ADCs have a 2-bit overflow detection, and
an underflow detection for U and V, to be used for AGC
control. The 2 bits are coded for one in-range level and
three overflow levels; 1 dB, 1 to 2 dB and 2 to 3 dB.
7.2
Digital processing blocks
7.2.1
O
VERFLOW DETECTION
A histogram of the three overflow levels is made every field
and can be read in a 2-byte accuracy. An input selector
defines which ADC is monitored.
In the event of U or V selection the underflow information
is also added to the first histogram level, in this way the
data can be handled as out-of-range information.
The histogram content provides information for the AGC to
make an accurate estimate of the decrease in gain, in the
event of overflow for luminance or out-of-range detection
for U and V.
7.2.2
Y
DELAY
The Y samples can be shifted onto 4 positions with
respect to the UV samples. This shift is meant to account
for a possible difference in delay prior to the SAA4978H,
e.g. from a prefilter in front of an analog-to-digital
converter. The zero delay setting is suitable for the
nominal case of aligned input data according to the
interface format standard. One setting provides one
sampleless delay in Y, the other two settings provide more
delay in the Y path.
7.2.3
T
RANSIENT NOISE SUPPRESSION
A circuit is added in the luminance channel to suppress the
typical multi-step trip level noise. This majority follower
filter compares the neighbouring pixels to a +1 or
1 LSB
difference. If the majority of these differences is +1 then 1
is added to the actual pixel. If the majority of these
differences is
1 then 1 is subtracted from the actual pixel.
The number of pixels included in the filter is selectable;
1 (bypass), 3, 5, 7 or 9.
7.2.4
N
ON
-
LINEAR PHASE FILTER AFTER
ADC
The non-linear phase filter adjusts for possible group delay
differences in the luminance channel. The filter coefficients
are [
L
×
(1
u); 1 + L;
L
×
u]; where L determines the
strength of the filter and u determines the asymmetry.
The effect of the asymmetry is that for higher frequencies
the delay is decreased for u
≤
0.5. Settings are provided
for L = 0,
1
16
,
2
16
and
3
16
and u = 0,
1
4
and
1
2
.
7.2.5
4 MH
Z NOTCH
The 4 MHz notch provides a zero on
1
4
of the sample
frequency. With f
s
= 16 MHz the notch is thus at 4 MHz.
The 3 dB notch width is 2 MHz. The filter coefficients are
1
8
×
[
1; 0; 5; 0; 5; 0;
1]. This filter gives a relative gain of
0.75 dB at 1.7 and 6.3 MHz.
The notch can be bypassed without changing the group
delay.
7.2.6
D
IGITAL CLAMP CORRECTION FOR
UV
During 32 samples within the active clamping the clamp
error is measured and accumulated to determine a
low-pass filtered value of the clamp error. A vertical
recursive filter is then used to further reduce this error
value. This value can be read by the microcontroller or be
used directly to correct the clamp error. It is also possible
for the microcontroller to give a fixed correction value.
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