參數(shù)資料
型號: SAA4978
廠商: NXP Semiconductors N.V.
英文描述: Picture Improved Combined Network PICNIC
中文描述: 圖片改進聯(lián)合網(wǎng)絡野餐
文件頁數(shù): 30/56頁
文件大小: 296K
代理商: SAA4978
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3
P
P
P
(
S
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BORDER_BAR_V_WIDTH
BORDER_REPEAT_H
BORDER_REPEAT_V
BORDER_Y
BORDER_U
36F
370
371
372
373
write
write
write
write
write
X X X X X X X X X width of vertical bars
X X X X X X X X horizontal repeat value
X X X X X X X X X vertical repeat value
X X X X X X X X Y value of sides and bars
X X X X X X X X U value of sides and bars
(twos complement)
BORDER_V
374
write
X X X X X X X X V value of sides and bars
(twos complement)
PLL
PLL_CK_AND_CD
PLL_CK
PLL_CD
PLL_IDTO_PLUS_VARIOUS
PLL_IDTO(18-16)
375
write
V
V
V
X X X X X X X X
X X X X X K factor control (0 to 31)
X X X
X X X
X X X
X X X increment offset for DTO bits 18 to 16
(twos complement; bit 18 is the sign
bit)
X
PLL off; keep output frequency
(off, on)
X
PLL open loop mode (closed, open)
X
do snapshot
X X X X X X X X increment offset for DTO bits 15 to 8
X X X X X X X X increment offset for DTO bits 7 to 0;
transfers all bits (18 to 0)
X X X skew transferred:
512
×
(1 + PLL_SKEW_DELAY)
clocks after HREF;
PLL_SKEW_DELAY (0 to 7)
X X X X X X X X maximum phase offset during field
HIGH byte
X X X X X X X X maximum phase offset during field
LOW byte; transfers all bits (15 to 0)
X X X X X X X X minimum phase offset during field
HIGH byte
damping control (0 to 7)
376
write
V
PLL_OFF
PLL_OPEN
DO_SNAP
PLL_IDTO(15-8)
PLL_IDTO(7-0)
V
377
378
write
write
V
V
PLL_SKEW_DELAY
379
write
PLL_PE_MAX(15-8)
325
read
V
PLL_PE_MAX(7-0)
326
read
V
PLL_PE_MIN(15-8)
327
read
V
NAME
ADDRESS
HEX
READ/
WRITE
DOUBLE
BUFFERED
(1)
8
7
6
5
4
3
2
1
0
DESCRIPTION
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