參數(shù)資料
型號(hào)： S71GL256NB0
廠商： Spansion Inc.
英文描述： Stacked Multi-chip Product (MCP)
中文描述： 堆疊式多芯片產(chǎn)品（MCP）
文件頁數(shù)： 96/147頁
文件大?。?/td> 1655K
代理商： S71GL256NB0
96
S29GLxxxN MirrorBit
TM
Flash Family
S29GLxxxN_00_A4 June 14, 2004
A d v a n c e I n f o r m a t i o n
Erase And Programming Performance
Notes:
1. Typical program and erase times assume the following conditions: 10,000 cycles, 25°C, 3.0 V V
CC
, checkerboard
pattern.
2. Under worst case conditions of 100,000 cycles, 90°C, V
CC
= 3.0 V.
3. Effective write buffer specification is based upon a 16-word write buffer operation.
4. The typical chip programming time is considerably less than the maximum chip programming time listed, since most
words program faster than the maximum program times listed.
5. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program
command. See Table 17 for further information on command definitions.
TSOP Pin and BGA Package Capacitance
Notes:
1. Sampled, not 100% tested.
2. Test conditions T
A
= 25°C, f = 1.0 MHz.
Parameter
Typ
(Note 1)
Max
(Note 2)
Unit
Comments
Sector Erase Time
TBD
TBD
sec
Excludes 00h
programming
prior to erasure (Note 5)
Chip Erase Time
S29GL128N
TBD
TBD
sec
S29GL256N
TBD
TBD
S29GL512N
TBD
TBD
Total Write Buffer Time
(Note 3)
TBD
TBD
μs
Excludes system level
overhead (Note 6)
Total Accelerated Effective
Write Buffer Programming
Time (Note 3)
TBD
TBD
μs
Chip Program Time
S29GL128N
TBD
TBD
sec
S29GL256N
TBD
TBD
S29GL512N
TBD
TBD
Parameter Symbol
Parameter Description
Test Setup
Typ
Max
Unit
C
IN
Input Capacitance
V
IN
= 0
TSOP
6
7.5
pF
C
OUT
Output Capacitance
V
OUT
= 0
TSOP
8.5
12
pF
C
IN2
Control Pin Capacitance
V
IN
= 0
TSOP
7.5
9
pF
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