參數(shù)資料
型號: S71GL256NB0
廠商: Spansion Inc.
英文描述: Stacked Multi-chip Product (MCP)
中文描述: 堆疊式多芯片產(chǎn)品(MCP)
文件頁數(shù): 85/147頁
文件大?。?/td> 1655K
代理商: S71GL256NB0
June 14, 2004 S29GLxxxN_00_A4
S29GLxxxN MirrorBit
TM
Flash Family
85
A d v a n c e I n f o r m a t i o n
AC Characteristics
Erase and Program Operations–S29GL512N Only
Notes:
1. Not 100% tested.
2. See the “AC Characteristics” section for more information.
3. For 1–16 words/1–32 bytes programmed.
4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
5. Unless otherwise indicated, AC specifications for 90 ns and 100 ns speed options are tested with V
IO
= V
CC
= 3 V.
AC specifications for 100 ns and 110 ns speed options are tested with V
IO
= 1.8 V and V
CC
= 3.0 V.
Parameter
Speed Options
JEDEC
Std.
Description
90
100
100
110
Unit
t
AVAV
t
WC
Write Cycle Time (Note 1)
Min
90
100
100
110
ns
t
AVWL
t
AS
Address Setup Time
Min
0
ns
t
ASO
Address Setup Time to OE# low during toggle
bit polling
Min
15
ns
t
WLAX
t
AH
Address Hold Time
Min
45
ns
t
AHT
Address Hold Time From CE# or OE# high
during toggle bit polling
Min
0
ns
t
DVWH
t
DS
Data Setup Time
Min
45
ns
t
WHDX
t
DH
Data Hold Time
Min
0
ns
t
OEPH
Output Enable High during toggle bit polling
Min
20
ns
t
GHWL
t
GHWL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
t
ELWL
t
CS
CE# Setup Time
Min
0
ns
t
WHEH
t
CH
CE# Hold Time
Min
0
ns
t
WLWH
t
WP
Write Pulse Width
Min
35
ns
t
WHDL
t
WPH
Write Pulse Width High
Min
30
ns
t
WHWH1
t
WHWH1
Write Buffer Program Operation (Notes 2, 3)
Typ
TBD
μs
Effective Write Buffer Program
Operation (Notes 2, 4)
Per Word
Typ
TBD
μs
Accelerated Effective Write Buffer
Program Operation (Notes 2, 4)
Per Word
Typ
TBD
μs
Program Operation (Note 2)
Word
Typ
TBD
μs
Accelerated Programming
Operation (Note 2)
Word
Typ
TBD
μs
t
WHWH2
t
WHWH2
Sector Erase Operation (Note 2)
Typ
TBD
sec
t
VHH
V
HH
Rise and Fall Time (Note 1)
Min
250
ns
t
VCS
V
CC
Setup Time (Note 1)
Min
50
μs
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