參數(shù)資料
型號(hào)： S71GL256NB0
廠(chǎng)商： Spansion Inc.
英文描述： Stacked Multi-chip Product (MCP)
中文描述： 堆疊式多芯片產(chǎn)品（MCP）
文件頁(yè)數(shù)： 128/147頁(yè)
文件大?。?/td> 1655K
代理商： S71GL256NB0
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128
pSRAM Type 7
pSRAM_Type07_13_A0 May 4, 2004
A d v a n c e I n f o r m a t i o n
Functional Description
Legend:
L = V
IL
, H = V
IH
, X can be either V
IL
or V
IH
, High-Z = High Impedence.
Notes:
1. Should not be kept this logic condition longer than 1ms. Please contact local Spansion representative for the relaxation of
1ms limitation.
2. Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. Data retention depends on the
selection of Power Down Program, 16M has data retetion in all modes except Power Down. Refer to POWER DOWN for the
detail.
3. Can be either V
IL
or V
IH
but must be valid before Read or Write.
4. OE# can be V
IL
during Write operation if the following conditions are satisfied:
(1) Write pulse is initiated by CE1# (refer to CE1# Controlled Write timing), or cycle time of the previous operation cycle is
satisfied.
(2) OE# stays V
IL
during Write cycle
Power Down (for 32M, 64M Only)
Power Down
The Power Down is low power idle state controlled by CE2. CE2 Low drives the
device in power down mode and maintains low power idle state as long as CE2 is
kept Low. CE2 High resumes the device from power down mode. These devices
have three power down mode. These can be proammed by series of read/write
operation. Each mode has follwoing features.
V
SS
Ground
Mode
CE2#
CE1#
WE#
OE#
LB#
UB#
A
21-0
DQ
8-1
DQ
16-9
Standby (Deselect)
H
H
X
X
X
X
X
High-Z
High-Z
Output Disable (Note 1)
H
L
H
H
X
X
Note 3
High-Z
High-Z
Output Disable (No Read)
H
L
H
H
Valid
High-Z
High-Z
Read (Upper Byte)
H
L
Valid
High-Z
Output Valid
Read (Lower Byte)
L
H
Valid
Output Valid
High-Z
Read (Word)
L
L
Valid
Output Valid
Output Valid
No Write
L
H (Note 4)
H
H
Valid
Invalid
Invalid
Write (Upper Byte)
H
L
Valid
Invalid
Input Valid
Write (Lower Byte)
L
H
Valid
Input Valid
Invalid
Write (Word)
L
L
Valid
Input Valid
Input Valid
Power Down
L
X
X
X
X
X
X
High-Z
High-Z
32M
64M
Mode
Retention Data
Retention Address
Mode
Retention Data
Retention Address
Sleep (default)
No
N/A
Sleep (default)
No
N/A
4M Partial
4M bit
00000h to 3FFFFh
8M Partial
8M bit
00000h to 7FFFFh
8M Partial
8M bit
00000h to 7FFFFh
16M Partial
16M bit
00000h to FFFFFh
Pin Name
Description
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參數(shù)描述
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