參數(shù)資料
型號: S71GL256NB0
廠商: Spansion Inc.
英文描述: Stacked Multi-chip Product (MCP)
中文描述: 堆疊式多芯片產(chǎn)品(MCP)
文件頁數(shù): 120/147頁
文件大?。?/td> 1655K
代理商: S71GL256NB0
120
pSRAM Type 1
pSRAM_Type01_12_A1 August 30, 2004
A d v a n c e I n f o r m a t i o n
Power Savings Modes (For 16M Page Mode, 32M and 64M Only)
There are several power savings modes.
Partial Array Self Refresh
Temperature Compensated Refresh (64M)
Deep Sleep Mode
Reduced Memory Size (32M, 16M)
The operation of the power saving modes ins controlled by the settings of bits
contained in the Mode Register. This definition of the Mode Register is shown in
Figure 28 and the various bits are used to enable and disable the various low
power modes as well as enabling Page Mode operation. The Mode Register is set
by using the timings defined in Figure xxx.
Partial Array Self Refresh (PAR)
In this mode of operation, the internal refresh operation can be restricted to a
16Mb, 32Mb, or 48Mb portion of the array. The array partition to be refreshed is
determined by the respective bit settings in the Mode Register. The register set-
tings for the PASR operation are defined in Table xxx. In this PASR mode, when
ZZ# is active low, only the portion of the array that is set in the register is re-
Figure 27. Timing Waveform of Page Mode Write Cycle (ZZ# = V
IH
)
Page Address
(A4 - A20)
LB#, UB#
WE#
t
WP
t
CW
t
DW
High-Z
Data Out
t
LBW,
t
UBW
CE#
Word Address
(A0 - A3 )
t
WC
t
PWC
t
DH
t
PDW
t
PDH
t
PDW
t
PDH
t
AS
t
PGMAX
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