參數(shù)資料
型號： S71GL128NB0
廠商： Spansion Inc.
英文描述： Stacked Multi-chip Product (MCP)
中文描述： 堆疊式多芯片產(chǎn)品（MCP）
文件頁數(shù)： 24/147頁
文件大?。?/td> 1655K
代理商： S71GL128NB0
24
S29GLxxxN MirrorBit
TM
Flash Family
S29GLxxxN_00_A4 June 14, 2004
A d v a n c e I n f o r m a t i o n
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the memory
content occurs during the power transition. No command is necessary in this
mode to obtain array data. Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data on the device data
outputs. The device remains enabled for read access until the command register
contents are altered.
See “Reading Array Data” for more information. Refer to the AC Read-Only Op-
erations table for timing specifications and to Figure 11 for the timing diagram.
Refer to the DC Characteristics table for the active current specification on read-
ing array data.
Page Mode Read
The device is capable of fast page mode read and is compatible with the page
mode Mask ROM read operation. This mode provides faster read access speed for
random locations within a page. The page size of the device is 8 words/16 bytes.
The appropriate page is selected by the higher address bits A(max)–A3. Address
bits A2–A0 in word mode (A2–A-1 in byte mode) determine the specific word
within a page. This is an asynchronous operation; the microprocessor supplies
the specific word location.
The random or initial page access is equal to t
ACC
or t
CE
and subsequent page
read accesses (as long as the locations specified by the microprocessor falls
within that page) is equivalent to t
PACC
. When CE# is de-asserted and reasserted
for a subsequent access, the access time is t
ACC
or t
CE
. Fast page mode accesses
are obtained by keeping the “read-page addresses” constant and changing the
“intra-read page” addresses.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data
to the device and erasing sectors of memory), the system must drive WE# and
CE# to V
IL
, and OE# to V
IH
.
The device features an
Unlock Bypass
mode to facilitate faster programming.
Once the device enters the Unlock Bypass mode, only two write cycles are re-
quired to program a word or byte, instead of four. The “Word/Byte Program
Command Sequence” section has details on programming data to the device
using both standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device.
Table 2 indicates the address space that each sector occupies.
Refer to the DC Characteristics table for the active current specification for the
write mode. The AC Characteristics section contains timing specification tables
and timing diagrams for write operations.
Write Buffer
Write Buffer Programming allows the system write to a maximum of 16 words/32
bytes in one programming operation. This results in faster effective programming
time than the standard programming algorithms. See “Write Buffer” for more
information.
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相關代理商/技術參數(shù)
參數(shù)描述
S71GL128NC0 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-chip Product (MCP)
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S71GL256NC0 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-chip Product (MCP)
S71GL512NB0 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-chip Product (MCP)
S71GL512NC0 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-chip Product (MCP)
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