參數(shù)資料
型號: S71GL128NB0
廠商: Spansion Inc.
英文描述: Stacked Multi-chip Product (MCP)
中文描述: 堆疊式多芯片產(chǎn)品(MCP)
文件頁數(shù): 127/147頁
文件大小: 1655K
代理商: S71GL128NB0
May 4, 2004 pSRAM_Type07_13_A0
pSRAM Type 7
127
A d v a n c e I n f o r m a t i o n
pSRAM Type 7
16Mb (1M word x 16-bit)
32Mb (2M word x 16-bit)
64Mb (4M word x 16-bit)
CMOS 1M/2M/4M-Word x 16 bit Fast Cycle Random Access Memory with Low
Power SRAM Interface
Features
Asynchronous SRAM Interface
Fast Access Time
— tCE = tAA = 60ns max (16M)
— tCE = tAA = 65ns max (32M/64M)
8 words Page Access Capability
— tPAA = 20ns max (32M/64M)
Low Voltage Operating Condition
— VDD = +2.7V to +3.1V
Wide Operating Temperature
— TA = -30°C to +85°C
Byte Control by LB and UB
Low Power Consumption
— IDDA1 = 20mA max (16M)
— IDDA1 = 30mA max (32M)
— IDDA1 =TBDmA max (64M)
— IDDS1 = 100μA max (16M)
— IDDS1 = 80μA max (32M)
— IDDS1 = TBDμA max (64M)
Various Power Down mode
— Sleep, 4M-bit Partial or 8M-bit Partial (32M)
— Sleep, 8M-bit Partial or 16M-bit Partial (64M
Pin Description
Pin Name
Description
A
21
to A
0
Address Input : A
19
to A
0
for 16M, A
20
to A
0
for 32M, A
21
to A
0
for 64M
CE1#
Chip Enable (Low Active)
CE2#
Chip Enable (High Active)
WE#
Write Enable (Low Active)
OE#
Output Enable (Low Active)
UB#
Upper Byte Control (Low Active)
LB#
Lower Byte Control (Low Active)
DQ
16
-
9
Upper Byte Data Input/Output
DQ
8
-
1
Lower Byte Data Input/Output
V
DD
Power Supply
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