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參數(shù)資料
| 型號： | S6D0114 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 132 RGB X 176 DOT 1-CHIP DRIVER IC WITH INTERNAL GRAM FOR 262,144 Colors TFT-LCD |
| 中文描述： | 132的RGB × 176交通部1 -芯片驅(qū)動器集成電路的26萬色TFT內(nèi)部革蘭氏液晶顯示器 |
| 文件頁數(shù)： | 82/143頁 |
| 文件大?。?/td> | 1919K |
| 代理商： | S6D0114 |
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132-RGB X 176-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY
S6D0114
Preliminary
82
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Internal clock frequency (fosc) [Hz] = Frame freq.
×
(Display raster-row (NL) + Front porch (FP) + Back porch (BP))
×
16-Clock
×
Fluctuation
Minimum speed for RAM writing [Hz] > 176
×
Display raster-row (NL)
/ {((Back porch (BP) + Display raster-row (NL) – Margin)
×
16 Clock) / fosc}
NOTE
: When RAM writing does not start immediately after the falling edge of VSYNC, the time between the falling edge of VSYNC and the RAM
writing start timing must also be considered.
-------------------------------------------------------------------------------------------------------------------------------------------------------
An example is shown below.
Example
Display size
132RGB
×
176 raster-rows
Display line number
176 raster-row (NL=10101)
Back/Front porch
3/5 raster-rows (BP=0011/FP=0101)
Frame Frequency
60Hz
Internal clock frequency (fosc) [Hz]= 60 Hz
×
(176 + 2 + 14)
×
16 clock
×
1.1 / 0.9 = 216 kHz
NOTES
:
1. Calculating the internal clock frequency requires considering the fluctuation. In the above case a 10%
Fluctuation within the VSYNC period is assumed.
2. The fluctuation includes LSI production variation and air temperature fluctuation. Other fluctuations,
including those for the external resistors and the supplied power, are not included in this example. Please keep in mind that a
margin for these factors is also needed.
Minimum speed for RAM writing [Hz] > 132
×
176 / {((3 + 176 – 5) raster-rows
×
16 clock) / 216kHz} = 1.8 MHz
NOTES
:
3. In this case RAM writing starts immediately after the falling edge of VSYNC.
4. The margin for display raster-row should be two raster-rows or more at the completion of RAM writing
for one frame.
Therefore, when RAM writing starting immediately after the falling edge of VSYNC is performed at 1.8 MHz or more,
the data for display can be rewritten before display operation starts. This means that flicker-free display operation is
achieved.
Display
(176-line)
Blanking period
Back porch (5-line)
Front porch (3-line)
RAM
write
Displaying
operation
VSYNC
[Line]
176
0
executed
line
2.32
12.90
13.04
16.74
(60Hz)
Back porch
14H
VSYNC
RAM write(10MHz)
23232 times
RAM write
1.8MHz
Displaying
operation
RC oscillation
±
10%
Displaying
operation
Figure 51. Operation for VSYNC Interface
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