參數資料
型號： S6D0114
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 132 RGB X 176 DOT 1-CHIP DRIVER IC WITH INTERNAL GRAM FOR 262,144 Colors TFT-LCD
中文描述： 132的RGB × 176交通部1 -芯片驅動器集成電路的26萬色TFT內部革蘭氏液晶顯示器
文件頁數： 18/143頁
文件大小： 1919K
代理商： S6D0114
132-RGB X 176-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY
S6D0114
Preliminary
18
FUNCTIONAL DESCRIPTION
SYSTEM INTERFACE
The S6D0114 has five high-speed system interfaces: an 80-system 18-/16-/9-/8-bit bus, a 68-system 18-/16-/9-/8-
bit bus, and a serial interface (SPI: Serial Peripheral Interface). The IM3-0 pins select the interface mode.
The S6D0114 has three 18-bit registers: an index register (IR), a write data register (WDR), and a read data register
(RDR). The IR stores index information for control register and GRAM. The WDR temporarily stores data to be
written into control register and GRAM. The RDR temporarily stores data read from GRAM. Data written into the
GRAM from MPU is initially written to the WDR and then written to the GRAM automatically. Data is read through the
RDR when reading from the GRAM, and the first read data is invalid and the second and the following data are valid.
When a logic operation is performed inside of the S6D0114 by using the display data stored in the GRAM and the
data written from the MPU, the data read through the RDR is used. Accordingly, the MPU does not need to read data
twice or to fetch the read data into the MPU. This enables high-speed processing.
Execution time for instruction, except oscillation start, is 0-clock cycle so that instructions can be written in
succession.
Table 10. Register Selection (18-/16-/9-/8- Parallel Interface)
SYSTEM
R/W
/WR
0
1
0
1
0
1
0
1
E
/RD
1
1
1
1
1
0
1
0
RS
Operations
0
0
1
1
0
0
1
1
Write index to IR
Read internal status
Write to control register and GRAM through WDR
Read from GRAM through RDR
Write index to IR
Read internal status
Write to control register and GRAM through WDR
Read from GRAM through RDR
68
80
Table 11. CSB/VLD signal (GRAM update control)
CSB
0
1
0
1
VLD
0
0
1
1
Operation
Data is written to GRAM, GRAM address is updated
Data is not written to GRAM, GRAM address is not updated
Data is not written to GRAM, GRAM address is updated
Data is not written to GRAM, GRAM address is not updated
Table 12. Register Selection (Serial Peripheral Interface)
R/W bit
0
1
0
1
RS bit
0
0
1
1
Operation
Write index to IR
Read internal status
Write data to control register and GRAM through WDR
Read data from GRAM through RDR
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