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參數(shù)資料
| 型號： | S5335QFAAB |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI Bus Controller, 3.3V |
| 中文描述： | PCI BUS CONTROLLER, PQFP176 |
| 封裝： | LQFP-176 |
| 文件頁數(shù)： | 86/189頁 |
| 文件大?。?/td> | 1193K |
| 代理商： | S5335QFAAB |
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S5335 – PCI Bus Controller, 3.3V
Revision 5.01 – November 30, 2005
Data Sheet
AMCC Confidential and Proprietary
DS1657 86
LOADING FROM SERIAL NV MEMORIES
SNV tied high indicates that a serial nv memory (or no
external device) is present. When serial nv memories
are used, data transfer is performed through a two-
wire, bidirectional data transfer protocol as defined by
commercial serial EEPROM/Flash offerings. These
devices have the advantages of low pin counts, small
package size, and economical price.
A serial nv memory is considered valid if the first serial
accesses contain the correct per-byte acknowledg-
ments (see Figure 41). If the serial per-byte
acknowledgment is not observed, the S5335 deter-
mines that no external serial nv memory is present
and the AMCC default Configuration Register values
are used.
Two pins are used to transfer data between the S5335
PCI controller and the external serial memory: a serial
clock pin, SCL, and a serial data pin, SDA. The serial
clock pin is an output from the S5335, and the serial
data pin is bidirectional. The serial clock is derived by
dividing the PCI bus clock by 512. This means that the
frequency of the serial clock is approximately 65 kHz
for a 33-MHz PCI bus clock.
Note: When a serial boot device is used, EA9 is de-
fined as a SCL divide by control pin.
If EA9 = 1 then SCL = PCLK/512
If EA9 = 0 then SCL = PCLK/8
This pin should be pulled high.
Communications with the serial memory involve sev-
eral clock transitions. A start event signals the
beginning of a transaction and is immediately followed
by an address transfer. Each address/data transfer
consists of 8 bits of information followed by a 1-bit
acknowledgment. When the exchange is complete, a
stop event is issued. Figure 39 shows the unique rela-
tionship defining both a start and stop event. Figure 40
shows the required timing for address/data with
respect to the serial clock.
For random accesses, the sequence involves one
clock to define the start of the sequence, eight clocks
to send the slave address and read/write command,
followed by a one-clock acknowledge, and so on. Fig-
ure 41 shows the sequence for a random write access
requiring 29 serial clock transitions. At the clock speed
for the S5335, this corresponds to one byte of data
transferred approximately every 0.5 milliseconds.
Read accesses may be either random or sequential.
Random read access requires a dummy write to load
the word address and require 39 serial clock transi-
tions. Figure 42 shows the sequence for a random
byte read.
To initialize the S5335 controller’s PCI Configuration
Registers, the smallest serial device necessary is a
128 x 8 organization. Although the S5335 controller
only requires 64 bytes, these bytes must begin at a 64-
byte address offset (0040h through 007Fh). This offset
constraint permits the configuration image to be
shared with a memory containing expansion BIOS
code and the necessary preamble to identify an
expansion BIOS. The largest serial device which may
be used is 2 Kbytes.
Table 51. Valid External Boot Memory Contents
Address
Data
Notes
0040h-41h
not FFFFh
This is the location that the S5335 PCI Controller will load a customized vendor ID. (FFFFh
is an illegal vendor ID.)
0050h
C2h, C1h or C0h
This is the least significant byte of the region which initializes the base address register #0
of the S5335 configuration register (Section 3.11). A value of C1h assigns the 16 DWORD
locations of the PCI operation registers into I/O space, a value of C0h defines memory
space, a value of C2h defines memory space below 1 Mbyte.
0051
FFh
Required.
0052h
E8h
Required.
0053h
10h
Required.
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