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參數(shù)資料
| 型號(hào)： | S5335QFAAB |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI Bus Controller, 3.3V |
| 中文描述： | PCI BUS CONTROLLER, PQFP176 |
| 封裝： | LQFP-176 |
| 文件頁數(shù)： | 103/189頁 |
| 文件大?。?/td> | 1193K |
| 代理商： | S5335QFAAB |
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S5335 – PCI Bus Controller, 3.3V
Revision 5.01 – November 30, 2005
Data Sheet
AMCC Confidential and Proprietary
DS1657 103
PCI BUS MASTERSHIP
When the S5335 requires PCI bus mastership, it pre-
sents a request via the REQ# signal. This signal is
connected to the system’s PCI bus arbiter.
Only one initiator (bus master) may control the PCI
bus at a given time. The bus arbiter determines which
initiator is given control of the bus. Control is granted
to a requesting device by the arbiter asserting that
device’s grant signal (GNT#). Each REQ#/ GNT# sig-
nal pair is unique to a given PCI agent.
After asserting REQ#, the S5335 assumes bus owner-
ship on the first PCI clock edge where its GNT# input
is asserted along with FRAME# and IRDY# deas-
serted (indicating no other device is generating PCI
bus cycles). Once ownership is established by the
S5335, it maintains ownership as long as the arbiter
keeps its GNT# asserted. If GNT# is deasserted, the
S5335 completes the current transaction.
The S5335 does this by deasserting FRAME# and
then deasserting IRDY# upon data transfer. Figure 59
shows a sequence where the S5335 is granted owner-
ship of the bus and then is preempted by another
master before the S5335 can finish its current
transaction.
Bus Mastership Latency Components
It is often necessary for system designers to predict
and guarantee that a minimum data transfer rate is
sustainable to support a particular application. In the
design of a bus mastering application, knowledge of
the maximum delay a device might encounter from the
time it requests the PCI bus to the time in which it is
actually granted the bus is desirable. This allows the
design to provide adequate data buffering. The PCI
specification refers to this bus request to grant delay
as “arbitration latency.”
Once a PCI initiator has been granted the bus, the PCI
specification defines the delay from the grant to the
new initiator’s assertion of FRAME# as the “bus acqui-
sition latency.” Afterwards, the delay from FRAME#
asserted to target ready (TRDY#) asserted is defined
as “target latency.” Figure 60 shows a time-line depict-
ing the components of PCI bus access latency.
There are numerous configuration variations possible
with the PCI specification. A system designer can
determine whether a bus master can support a critical,
timely transfer by establishing a specific configuration
and by defining these latency values. The S5335, as
an initiator, produces the fastest response allowable
for its bus acquisition latency (GNT# to FRAME#
asserted). The S5335 also implements the PCI Master
Latency Timer. Once granted the bus, the S5335 is
guaranteed ownership for a minimum amount of time
defined by the Master Latency Timer. The S5335, as
an initiator, cannot control the responsiveness of a
particular target nor the bus arbitration delay.
The PCI specification provides two mechanisms to
control the amount of time a master may own the bus.
One mechanism is through the master (masterinitiated
termination). The other is by the target and is achieved
through a target-initiated disconnect.
Bus Arbitration
Although the PCI specification defines the condition
that constitutes bus ownership, it does not provide
rules to be used by the system’s PCI bus arbiter in
deciding which master is to be granted the PCI bus
next. The arbitration priority scheme implemented by a
system may be fixed, rotational, or custom. The arbi-
tration latency is a function of the system, not the
S5335.
Figure 60. PCI Bus Access Latency Components
Bus Access Latency
REQ#
Asserted
GNT#
Asserted
FRAME#
Asserted
TRDY#
Asserted
--Arbitration Latency--
--Bus Acquisition--
Latency
--Target Latency--
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