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參數(shù)資料
| 型號： | S5335QFAAB |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI Bus Controller, 3.3V |
| 中文描述： | PCI BUS CONTROLLER, PQFP176 |
| 封裝： | LQFP-176 |
| 文件頁數(shù)： | 46/189頁 |
| 文件大?。?/td> | 1193K |
| 代理商： | S5335QFAAB |
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S5335 – PCI Bus Controller, 3.3V
Revision 5.01 – November 30, 2005
Data Sheet
AMCC Confidential and Proprietary
DS1657 46
Table 37. Base Address Register — Memory (Bit 0 = 0)
Bit
Description
31:4
Base Address Location. These bits are used to position the decoded region in memory space. Only bits which return
a 1 after being written as 1 are usable for this purpose. Except for Base Address Register 0, these bits are individually
enabled by the contents sourced from the external boot memory.
3
Prefetchable. When set as a 1, this bit signifies that this region of memory can be cached. Cachable regions can only
operations will return the data associated for all bytes regardless of the Byte Enables. Memory space which cannot
support this behavior should leave this bit in the zero state. For Base Addresses 1 through 4, this bit is set by the
Reset pin and later initialized by the external boot memory (if present). Base Address Register 0 always has this bit
set to 0. This bit is read only from the PCI interface.
2:1
Memory Type. These two bits identify whether the memory space is 32 or 64 bits wide and if the space location is
restricted to be within the first megabyte of memory space. The table below describes the encoding:
Bits
Description
2 1
0 0
Region is 32 bits wide and can be located anywhere in 32 bit memory space.
0 1
Region is 32 bits wide and must be mapped below the first MByte of memory space.
1 0
Region is 64 bits wide and can be mapped anywhere within 64 bit memory space. (Not sup-
ported by this controller.)
1 1
Reserved. (Not supported by this controller.)
1
The 64-bit memory space is not supported by this controller, so bit 2 should not be set. The only meaningful option is
whether it is desired to position memory space anywhere within 32-bit memory space or restrain it to the first mega-
byte. For Base Addresses 1 through 5, this bit is set by the reset pin and later initialized by the external boot memory
(if present).
0
Space Indicator = 0. When set to 0, this bit identifies a base address region as a memory space and the remaining
bits in the base address register are defined as shown in Table 38.
Table 38. Base Address Register — I/O (Bit 0 = 1)
Bit
Description
31:2
Base Address Location. These bits are used to position the decoded region in I/O space. Only bits which return a “1”
after being written as “1” are usable for this purpose. Except for Base Address 0, these bits are individually enabled
by the contents sourced from the external boot memory (EPROM or nvRAM).
1
Reserved. This bit should be zero. (Note: disabled Base Address Registers will return all zeros for the entire register
location, bits 31 through 0).
0
Space Indicator = 1. When one this bit identifies a base address region as an I/O space and the remaining bits in the
base address register have the definition as shown in Figure 18.
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