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參數(shù)資料
| 型號： | S5335QFAAB |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI Bus Controller, 3.3V |
| 中文描述： | PCI BUS CONTROLLER, PQFP176 |
| 封裝： | LQFP-176 |
| 文件頁數(shù)： | 112/189頁 |
| 文件大?。?/td> | 1193K |
| 代理商： | S5335QFAAB |
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S5335 – PCI Bus Controller, 3.3V
Revision 5.01 – November 30, 2005
Data Sheet
AMCC Confidential and Proprietary
DS1657 112
Asserting PTADR# is functionally identical to access-
ing the Pass-Thru address register with RD#,
SELECT#, BE[3:0]#, and ADR[6:2]. RD# and WR#
must be deasserted when PTADR# is asserted, but
SELECT# may be asserted. These inputs automati-
cally drive the address (internally) to 28h and assert all
byte enables. The ADR[6:2] and BE[3:0]# are ignored
when using the PTADR# direct access input. When
PTADR# is asserted, the contents of the APTA register
are immediately driven onto the Add-On data bus.
The PTADR# direct access signal accesses the Pass-
Thru address register as 16-bits or 32-bits, whatever
the MODE pin is configured for. For 16-bit mode,
PTADR# only presents the lower 16-bits of the APTA
register.
PTRDY# indicates that the Add-On has completed the
current Pass-Thru access. Multiple Add-On reads or
writes may occur to the Pass-Thru data (APTD) regis-
ter before asserting PTRDY#. This may be required for
8-bit or 16-bit Add-On interfaces using multiple
accesses to the 32-bit Pass-Thru data register. In
some cases, the Add-On bus may be 32-bits, but logic
may require multiple BPCLK periods to read or write
data. In this situation, accesses may be extended by
holding off PTRDY#. PTRDY# must be synchronized
to BPCLK.
NON-VOLATILE MEMORY INTERFACE
The S5335 allows read and write access to the nv
memory device used for configuration. Reads are nec-
essary during device initialization as configuration
information is downloaded into the S5335. If an expan-
sion BIOS is implemented in the nv memory, the host
transfers (shadows) the code into system DRAM.
Writes are useful for in-field updates to expansion
BIOS code. This allows software to update the nv
memory contents without altering hardware.
Non-Volatile Memory Interface Signals
For serial nv memory devices, there are only two sig-
nals used to interface with nv memory. SCL is the
serial clock, and SDA is the serial data line. The func-
tionality of these signals is described in-detail in the
PIN description Section of this book. The designer
does not need to generate the timings for SCL and
SDA. The S5335 automatically performs the correct
serial access when programmed for serial devices.
For byte-wide nv memory devices, there is an 8-bit
data bus (EQ7:0), and a 16-bit address bus (EA15:0)
dedicated for the nv memory interface. When a serial
nv memory is implemented, many of these pins have
alternate functions. The S5335 also has read (ERD#)
and write (EWR#) outputs to drive the OE# and WR#
inputs on a byte-wide nv memory. The designer does
not need to generate the timings for these outputs.
The S5335 automatically performs the read and write
accesses when programmed for byte wide devices.
Accessing Non-Volatile Memory
The nv memory, if implemented, can be accessed
through the PCI interface or the Add-On interface.
Accesses from both the PCI side and the Add-On side
must be synchronous with the PCI clock (BPCLK for
the Add-On). Accesses to the nv memory from the PCI
interface are through the Bus Master Control/Status
Register (MCSR) PCI Operation Register.
Accesses to the nv memory from the Add-On interface
are through the Add-On General Control/Status Regis-
ter (AGCSTS) Add-On Operation Register. Accesses
to the MCSR register are from the PCI bus and are,
therefore, automatically synchronous to the PCI clock.
Accesses to the AGCSTS register from the Add-On
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