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參數(shù)資料
| 型號： | S5335QFAAB |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI Bus Controller, 3.3V |
| 中文描述： | PCI BUS CONTROLLER, PQFP176 |
| 封裝： | LQFP-176 |
| 文件頁數(shù)： | 68/189頁 |
| 文件大小： | 1193K |
| 代理商： | S5335QFAAB |
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S5335 – PCI Bus Controller, 3.3V
Revision 5.01 – November 30, 2005
Data Sheet
AMCC Confidential and Proprietary
DS1657 68
Table 46. Bus Master Control/Status Register
Bit
Description
31:29
nvRAM Access Control. This field provides a method for access to the optional external non-volatile memory. Write
operations are achieved by a sequence of byte operations involving these bits and the 8-bit field of bits 23 through
16. The sequence requires that the low-order address, high order address, and then a data byte are loaded in order.
Bit 31 of this field acts as a combined enable and ready for the access to the external memory. D31 must be written
to a 1 before an access can begin, and subsequent accesses must wait for bit D31 to become zero (ready).
D31
D30
D29
W/R
0
X
X
W
Inactive
1
0
0
W
Load low address byte
1
0
1
W
Load high address byte
1
1
0
W
Begin write
1
1
1
W
Begin read
0
X
X
R
Ready
1
X
X
R
Busy
Cautionary note: The nonvolatile memory interface is also available for access by the Add-On interface. Accesses
by both the Add-On and PCI bus to the nv memory are not directly supported by the S5335 device. Software must
be designed to prevent the simultaneous access of nv memory to prevent data corruption within the memory and
provide for accurate data retrieval.
28
FIFO loop back mode.
27
Mailbox Flag Reset. Writing a one to this bit causes all mailbox status flags to become reset (EMPTY). It is not nec-
essary to write this bit as zero because it is used internally to produce a reset pulse. Since reading of this bit will
always produce zeros, this bit is write only.
26
Add-On to PCI FIFO Status Reset. Writing a one to this bit causes the Add-On to PCI (Bus master memory writes)
FIFO empty flag to set indicating empty and the FIFO FULL flag to reset and the FIFO Four Plus word flag to reset.
It is not necessary to write this bit as zero because it is used internally to produce a reset pulse. Since reading of this
bit will always produce zeros, this bit is write only.
25
PCI to Add-On FIFO Status Reset. Writing a one to this bit causes the PCI to Add-On (Bus master memory reads)
FIFO empty flag to set indicating empty and the FIFO FULL flag to reset and the FIFO Four Plus words available
flag to set. It is not necessary to write this bit as zero because it is used internally to produce a reset pulse. Since
reading of this bit will always produce zeros, this bit is write only.
24
Add-On pin reset. Writing a one to this bit causes the reset output pin to become active. Writing a zero to this pin is
necessary to remove the assertion of reset. This register bit is read/write.
23:16
Non-volatile memory address/data port. This 8-bit field is used in conjunction with bit 31, 30 and 29 of this register to
access the external non-volatile memory. The contents written are either low address, high address, or data as
defined by bits 30 and 29. This register will contain the external non-volatile memory data when the proper read
sequence for bits 31 through 29 is performed.
15
Enable memory read multiple during S5335 bus mastering mode.
14
Read Transfer Enable. This bit must be set to a one for S5335 PCI bus master read transfers to take place. Writing
a zero to this location will suspend an active transfer. An active transfer is one in which the transfer count is not zero.
13
Read FIFO management scheme. When set to a 1, this bit causes the controller to refrain from requesting the PCI
bus unless it has four or more vacant FIFO locations to fill. Once the controller is granted the PCI bus or is in pos-
session of the bus due to the write channel, this constraint is not meaningful. When this bit is zero the controller will
request the PCI bus if it has at least one vacant FIFO word.
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