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參數(shù)資料
| 型號： | S5335QFAAB |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI Bus Controller, 3.3V |
| 中文描述： | PCI BUS CONTROLLER, PQFP176 |
| 封裝： | LQFP-176 |
| 文件頁數(shù)： | 155/189頁 |
| 文件大?。?/td> | 1193K |
| 代理商： | S5335QFAAB |
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S5335 – PCI Bus Controller, 3.3V
Revision 5.01 – November 30, 2005
Data Sheet
AMCC Confidential and Proprietary
DS1657 155
Clock 0:
PCI address information is stored in the S5335 Pass-Thru Address Register. The PCI address is recognized as
an access to Pass-Thru region 1. PTATN# is asserted by the S5335 to indicate a Pass-Thru access is occurring.
PTBURST# is asserted by the S5335, indicating the current Pass-Thru read is a burst.
Clock 1:
Pass-Thru status signals indicate what action is required by Add-On logic. Pass-Thru status outputs are valid
when PTATN# is active and are sampled by the Add-On at the rising edge of clock 2.
PTBURST#
Deasserted, the S5335 does not yet recognize a PCI burst.
PTNUM[1:0] 01.
Indicates the PCI access is to Pass-Thru region 1.
PTWR
Deasserted. The Pass-Thru access is a read.
PTBE[3:0]#
0h. Indicate the Pass-Thru access is 32-bits.
The PTADR# input is asserted to read the Pass-Thru Address Register. The byte enable, address, and
SELECT# inputs are changed during this clock to select the Pass-Thru Data Register during clock cycle 3.
Clock 2:
SELECT#, byte enable, and the address inputs remain driven to read the Pass-Thru Data Register at offset
2Ch.
Clock 3:
WR# asserted at the rising edge of clock 3 writes DATA 1 into the S5335. PTRDY# asserted at the rising edge
of clock 3 completes the current data phase.
Clock 4:
Add-On logic drives DATA 2 on the Add-On bus, but PTRDY# deasserted at the rising edge of clock 4 extends
the current data phase.
Clock 5:
WR# asserted at the rising edge of clock 5 writes DATA 2 into the S5335. PTRDY# asserted at the rising edge
of clock 5 completes the current data phase.
Clock 6:
Add-On logic drives DATA 3 on the Add-On bus, but PTRDY# deasserted at the rising edge of clock 6 extends
the current data phase.
Clock 7:
WR# asserted at the rising edge of clock 7 writes DATA 3 into the S5335. PTRDY# asserted at the rising edge
of clock 7 completes the current data phase. On the PCI bus, IRDY# has been deasserted, causing PTATN# to
be deasserted. This is how a PCI initiator adds wait states, if it cannot read data quickly enough.
Clock 8:
PTATN# remains deasserted at the rising edge of clock 8. The Add-On cannot write DATA 4 until PTATN# is
asserted. Add-On logic continues to drive DATA 4 on the Add-On bus. PTATN# is reasserted during the cycle,
indicating the PCI initiator is done adding wait states.
Clock 9:
WR# asserted at the rising edge of clock 9 writes DATA 4 into the S5335. PTRDY# asserted at the rising edge
of clock 9 completes the current data phase.
Clock 10:
Add-On logic drives DATA 5 on the Add-On bus, but PTRDY# deasserted at the rising edge of clock 10 extends
the current data phase.
Clock 11:
PTATN# remains deasserted at the rising edge of clock 11. The Add-On does not have to write DATA 5 until
PTATN# is asserted. Add-On logic continues to drive DATA 5 on the Add-On bus. PTATN# is reasserted during
the cycle, indicating the PCI initiator is done adding wait states.
Clock 12:
PTRDY# asserted at the rising edge of clock 12 completes the final data phase. Any data written into the Pass-
Thru data register is not required and is never passed to the PCI interface (as PTRDY# is not asserted at the ris-
ing edge of clock 13).
Clock 13:
PTATN# and PTBURST# deasserted at the rising edge of clock 13 indicates the Pass-Thru access is complete.
The S5335 can accept new Pass-Thru accesses from the PCI bus at clock 14.
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相關代理商/技術參數(shù) |
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| S533-M04-F13A-E | 制造商:UNICORP 功能描述: |
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| S5340 | 制造商:BOTHHAND 制造商全稱:Bothhand USA, LP. 功能描述:T1/CEPT/ISDN-PRI TRANSFORMER |
| S5342 | 制造商:MERKLE-KORFF INDUSTRIES 功能描述:Old Colman P/N: RP4-8 |
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