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參數(shù)資料
| 型號(hào)： | S5335 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PCI Bus Controller, 3.3V |
| 中文描述： | PCI總線控制器，3.3 |
| 文件頁(yè)數(shù)： | 96/189頁(yè) |
| 文件大?。?/td> | 1193K |
| 代理商： | S5335 |
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S5335 – PCI Bus Controller, 3.3V
Revision 5.01 – November 30, 2005
Data Sheet
AMCC Confidential and Proprietary
DS1657 96
PCI Write Transfers
Write transfers on the PCI bus are one clock period
shorter than read transfers. This is because the
AD[31:0] bus does not require a turn-around cycle
between the address and data phases. When the
S5335 is accessed (target), it responds to a PCI bus
memory or I/O transfers. As a PCI initiator, the S5335
controller can also execute PCI memory write
operations.
The timing diagram in Figure 49 represents an S5335
initiator PCI write operation transferring to a fast, zero-
wait-state memory target. The signals driven by the
S5335 during the transfer are FRAME#, AD[31:0], C/
BE[3:0]#, and IRDY#. The signals driven by the target
are DEVSEL# and TRDY#. As with PCI reads, targets
assert DEVSEL# and TRDY# after the clock defining
the end of the address phase (boundary of clock peri-
ods 1 and 2 of Figure 49). TRDY# is not driven until
the target has accepted the data for the PCI write.
When the S5335 becomes the PCI initiator, it attempts
sustained zero-wait state burst writes until one of the
following occurs:
The memory target aborts the transfer
PCI bus grant (GNT# is removed)
The Add-On to PCI FIFO becomes empty
A higher priority (PCI to Add-On) S5335 trans-
fer is pending (if programmed for priority)
The write transfer byte count reaches zero
Bus mastering is disabled from the Add-On
interface
Write accesses to the S5335 operation registers
(S5335 as a target) are shown in Figure 50. Here, the
S5335 asserts the signal STOP# in clock period 3.
STOP# is asserted because the S5335 supports fast,
zero-wait-state write cycles but does not support burst
writes to operation registers. Wait states may be
added by the initiator by not asserting the signal
IRDY# during clock 2 and beyond. There is only one
condition where writes to S5335 operation registers do
not return TRDY# (but do assert STOP#). This is
called a target-initiated termination or target discon-
nect and occurs when a write attempt is made to a full
S5335 FIFO. As with the read transfers, the assertion
of STOP# without the assertion of TRDY# indicates
the initiator should retry the operation later.
Figure 49. Zero Wait State Burst Write PCI Bus Transfer (S5335 as Initiator)
PCI CLOCK
FRAME #
AD 31:0]
C/BE 3:0]#
IRDY#
TRDY#
DEVSEL#
ADDRESS
DATA 1
BYTE EN 1
1
2
3
4
(I)
(I)
(T)
(T)
(I)
(I)
BYTE EN 3
BYTE EN 2
DATA 2
DATA 3
* BUS COMMAND = MEMORY WRITE
DATA
TRANSFER
#1
DATA
TRANSFER
#2
DATA
TRANSFER
#3
6
BUS COMMAND*
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET
5
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S5335DK | PCI Bus Controller, 3.3V |
| S5335QF | PCI Bus Controller, 3.3V |
| S5335QFAAB | PCI Bus Controller, 3.3V |
| S5566B | General Purpose Rectifier(通用整流器) |
| S5566G | General Purpose Rectifier(通用整流器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5335DK | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Bus Controller, 3.3V |
| S5335QF | 制造商:AppliedMicro 功能描述: |
| S5335QFAAB | 制造商:AppliedMicro 功能描述:PCI Bus Controller |
| S533-M04-F13A-E | 制造商:UNICORP 功能描述: |
| S-533-M04-F13-F | 制造商:UNICORP 功能描述: |
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