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參數(shù)資料
| 型號(hào)： | S5335 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PCI Bus Controller, 3.3V |
| 中文描述： | PCI總線控制器，3.3 |
| 文件頁(yè)數(shù)： | 122/189頁(yè) |
| 文件大?。?/td> | 1193K |
| 代理商： | S5335 |
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S5335 – PCI Bus Controller, 3.3V
Revision 5.01 – November 30, 2005
Data Sheet
AMCC Confidential and Proprietary
DS1657 122
Once interrupts are enabled, the interrupt service routine must access the mailboxes and clear the interrupt
source. A particular application may not require all of the steps shown. For instance, a design may only use incom-
ing mailbox interrupts and not require support for outgoing mailbox interrupts. The interrupt service routine tasks
are shown below:
Enabling Add-On mailbox interrupts:
1. Enable Add-On outgoing mailbox interrupts. A specific byte within one of the outgoing mailboxes is identified to assert
IRQ# when read by the PCI interface.
AINT
Bit 12
Enable outgoing mailbox interrupts
AINT
Bits 11:10
Identify mailbox to generate interrupt
AINT
Bits 9:8
Identify mailbox byte to generate interrupt
2. Enable Add-On incoming mailbox interrupts. A specific byte within one of the incoming mailboxes is identified to assert
IRQ# when written by the PCI interface.
AINT
Bit 4
Enable incoming mailbox interrupts
AINT
Bits 3:2
Identify mailbox to generate interrupt
AINT
Bits 1:0
Identify mailbox byte to generate interrupt
With either the Add-On or PCI interface, these two steps can be performed with a single access to the appropriate register.
They are shown separately here for clarity.
Servicing a PCI mailbox interrupt (INTA#):
1. Identify the interrupt source(s). Multiple interrupt sources are available on the S5335. The interrupt service routine must
verify that a mailbox generated the interrupt (and not some other interrupt source).
INTCSR
Bit 16
PCI outgoing mailbox interrupt indicator
INTCSR
Bit 17
PCI incoming mailbox interrupt indicator
2. Check mailbox status. The mailbox status bits indicate which mailbox bytes must be read or written.
MBEF
Bits 31:16
Full PCI incoming mailbox bytes
MBEF
Bits 15:0
Empty PCI outgoing mailbox bytes
3. Access the mailbox. Based on the contents of MBEF, mailboxes are read or written. Reading an incoming mailbox byte
clears the corresponding status bit in MBEF.
OMBx
Bits 31:0
PCI outgoing mailboxes
IMBx
Bits 31:0
PCI incoming mailboxes
4. Clear the interrupt source. The PCI INTA# signal is deasserted by clearing the interrupt request. The request is cleared
by writing a ‘1’ to the appropriate bit.
INTCSR
Bit 16
Clear PCI outgoing mailbox interrupt
INTCSR
Bit 17
Clear PCI incoming mailbox interrupt
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S5335DK | PCI Bus Controller, 3.3V |
| S5335QF | PCI Bus Controller, 3.3V |
| S5335QFAAB | PCI Bus Controller, 3.3V |
| S5566B | General Purpose Rectifier(通用整流器) |
| S5566G | General Purpose Rectifier(通用整流器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5335DK | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Bus Controller, 3.3V |
| S5335QF | 制造商:AppliedMicro 功能描述: |
| S5335QFAAB | 制造商:AppliedMicro 功能描述:PCI Bus Controller |
| S533-M04-F13A-E | 制造商:UNICORP 功能描述: |
| S-533-M04-F13-F | 制造商:UNICORP 功能描述: |
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