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| 型號(hào)： | S5335 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PCI Bus Controller, 3.3V |
| 中文描述： | PCI總線控制器，3.3 |
| 文件頁(yè)數(shù)： | 56/189頁(yè) |
| 文件大?。?/td> | 1193K |
| 代理商： | S5335 |
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S5335 – PCI Bus Controller, 3.3V
Revision 5.01 – November 30, 2005
Data Sheet
AMCC Confidential and Proprietary
DS1657 56
Outgoing Mailbox Registers (OMB)
Register Names:
Outgoing Mailboxes 1-4
These four DWORD registers provide a method for sending command or
parameter data to the Add-On system. PCI bus operations to these regis-
ters may be in any width (byte, word, or DWORD). Writing to these regis-
ters can be a source for Add-On bus interrupts (if desired) by enabling
their interrupt generation through the use of the Add-On’s interrupt con-
trol/status register.
PCI Address Offset:
00h, 04h, 08h, 0Ch
Power-up value:
XXXXXXXXh
Attribute:
Read/Write
Size:
32 bits
Incoming Mailbox Registers (IMB)
Register Names:
Incoming Mailboxes 1-4
These four DWORD registers provide a method for receiving user
defined data from the Add-On system. PCI bus read operations to these
registers may be in any width (byte, word, or DWORD). Only read opera-
tions are supported. Reading from these registers can optionally cause
an Add-On bus interrupt (if desired) by enabling their interrupt generation
through the use of the Add-On’s interrupt control/status register. Mailbox
4, byte 3 only exists as device pins on the S5335 devices when used with
a serial nonvolatile memory.
PCI Address Offset:
10h, 14h, 18h, 1Ch
Power-up value:
XXXXXXXXh
Attribute:
Read Only
Size:
32 bits
FIFO Register Port (FIFO)
Register Name:
FIFO Port
This location provides access to the bidirectional FIFO. Separate regis-
ters are used when reading from or writing to the FIFO. Accordingly, it is
not possible to read what was written to this location. The FIFO registers
are implicitly involved in all bus master operations and, as such, should
not be accessed during active bus master transfers. When operating
upon the FIFOs with software program transfers involving word or byte
operations, the endian sequence of the FIFO should be established as
described under FIFO Endian Conversion Management in order to pre-
serve the internal FIFO data ordering and flag management. The FIFO’s
fullness may be observed by reading the master control-status register or
MCSR register.
PCI Address Offset:
20h
Power-up value:
XXXXXXXXh
Attribute:
Read/Write
Size:
32 bits
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S5335DK | PCI Bus Controller, 3.3V |
| S5335QF | PCI Bus Controller, 3.3V |
| S5335QFAAB | PCI Bus Controller, 3.3V |
| S5566B | General Purpose Rectifier(通用整流器) |
| S5566G | General Purpose Rectifier(通用整流器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5335DK | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Bus Controller, 3.3V |
| S5335QF | 制造商:AppliedMicro 功能描述: |
| S5335QFAAB | 制造商:AppliedMicro 功能描述:PCI Bus Controller |
| S533-M04-F13A-E | 制造商:UNICORP 功能描述: |
| S-533-M04-F13-F | 制造商:UNICORP 功能描述: |
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